format + module update

2025-10-13 22:06:51 -07:00
parent 54a199ca9c
commit 066d9ca99e
12 changed files with 109 additions and 139 deletions
--- a/src/peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv
+++ b/src/peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv
@@ -9,25 +9,49 @@
 `endif
 {% endif -%}

-//======================================================
-// APB Fanout
-//======================================================
+assign cpuif_req   = {{cpuif.signal("PSELx")}};
+assign cpuif_wr_en = {{cpuif.signal("PWRITE")}};
+assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
+assign cpuif_rd_en = !{{cpuif.signal("PWRITE")}};
+
 {%- for child in cpuif.addressable_children -%}
 {%- if child is array -%}
 for (genvar g_{{child.inst_name|lower}}_idx = 0; g_{{child.inst_name|lower}}_idx < N_{{child.inst_name|upper}}S; g_{{child.inst_name|lower}}_idx++) begin : g_passthrough_{{child.inst_name|lower}}
-    assign {{self.signal("PCLK", child, f"g_{child.inst_name.lower()}_idx")}}    = {{self.signal("PCLK")}};
-    assign {{self.signal("PRESETn", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PRESETn")}};
-    assign {{self.signal("PENABLE", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PENABLE")}};
-    assign {{self.signal("PWRITE", child, f"g_{child.inst_name.lower()}_idx")}}  = {{self.signal("PWRITE")}};
-    assign {{self.signal("PADDR", child, f"g_{child.inst_name.lower()}_idx")}}   = {{self.signal("PADDR")}} [{{child.addr_width - 1}}:0]; // FIXME: Check slicing
-    assign {{self.signal("PWDATA", child, f"g_{child.inst_name.lower()}_idx")}}  = {{self.signal("PWDATA")}};
+    assign {{cpuif.signal("PCLK", child, f"g_{child.inst_name.lower()}_idx")}}    = {{cpuif.signal("PCLK")}};
+    assign {{cpuif.signal("PRESETn", child, f"g_{child.inst_name.lower()}_idx")}} = {{cpuif.signal("PRESETn")}};
+    assign {{cpuif.signal("PSELx", child, f"g_{child.inst_name.lower()}_idx")}}    = (cpuif_wr_req[{{loop.indx}}] || cpuif_rd_req[{{loop.indx}}]) ? 1'b1 : 1'b0;
+    assign {{cpuif.signal("PENABLE", child, f"g_{child.inst_name.lower()}_idx")}} = {{cpuif.signal("PENABLE")}};
+    assign {{cpuif.signal("PWRITE", child, f"g_{child.inst_name.lower()}_idx")}}  = (cpuif_wr_req[{{loop.index}}]) ? 1'b1 : 1'b0;
+    assign {{cpuif.signal("PADDR", child, f"g_{child.inst_name.lower()}_idx")}}   = {{cpuif.get_address_slice(cpuif_wr_addr, child)}};
+    assign {{cpuif.signal("PWDATA", child, f"g_{child.inst_name.lower()}_idx")}}  = cpuif_wr_data;
+    assign cpuif_rd_ack[loop.index] = {{cpuif.signal("PREADY", child)}};
+    assign cpuif_rd_data[loop.index] = {{cpuif.signal("PRDATA", child)}};
+    assign cpuif_rd_err[loop.index] = {{cpuif.signal("PSLVERR", child)}};
 end
 {%- else -%}
-assign {{self.signal("PCLK", child)}}    = {{self.signal("PCLK")}};
-assign {{self.signal("PRESETn", child)}} = {{self.signal("PRESETn")}};
-assign {{self.signal("PENABLE", child)}} = {{self.signal("PENABLE")}};
-assign {{self.signal("PWRITE", child)}}  = {{self.signal("PWRITE")}};
-assign {{self.signal("PADDR", child)}}   = {{self.signal("PADDR")}} [{{child.addr_width - 1}}:0]; // FIXME: Check slicing
-assign {{self.signal("PWDATA", child)}}  = {{self.signal("PWDATA")}};
+assign {{cpuif.signal("PCLK", child)}}    = {{cpuif.signal("PCLK")}};
+assign {{cpuif.signal("PRESETn", child)}} = {{cpuif.signal("PRESETn")}};
+assign {{cpuif.signal("PSELx", child)}}    = (cpuif_wr_sel[{{loop.index0}}] || cpuif_rd_sel[{{loop.index0}}]) ? 1'b1 : 1'b0;
+assign {{cpuif.signal("PENABLE", child)}} = {{cpuif.signal("PENABLE")}};
+assign {{cpuif.signal("PWRITE", child)}}  = (cpuif_wr_req[{{loop.index}}]) ? 1'b1 : 1'b0;
+assign {{cpuif.signal("PADDR", child)}}   = {{cpuif.get_address_slice(cpuif_wr_addr, child)}};
+assign {{cpuif.signal("PWDATA", child)}}  = cpuif_wr_data;
+assign cpuif_rd_ack[loop.index] = {{cpuif.signal("PREADY", child)}};
+assign cpuif_rd_data[loop.index] = {{cpuif.signal("PRDATA", child)}};
+assign cpuif_rd_err[loop.index] = {{cpuif.signal("PSLVERR", child)}};
 {%- endif -%}
-{%- endfor -%}
+{%- endfor -%}
+
+always_comb begin
+    {{cpuif.signal("PREADY")}} = 1'b0;
+    {{cpuif.signal("PRDATA")}} = '0;
+    {{cpuif.signal("PSLVERR")}} = 1'b0;
+
+    for(int i = 0; i < {{cpuif.addressable_children | length}}; i++) begin
+        if (cpuif_rd_sel[i]) begin
+            {{cpuif.signal("PREADY")}} = cpuif_rd_ack[i];
+            {{cpuif.signal("PRDATA")}} = cpuif_rd_data[i];
+            {{cpuif.signal("PSLVERR")}} = cpuif_rd_err[i];
+        end
+    end
+end
--- a/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
+++ b/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
@@ -9,111 +9,53 @@
 `endif
 {% endif -%}

-//======================================================
-// APB Fanout
-//======================================================
+assign cpuif_req   = {{cpuif.signal("PSELx")}};
+assign cpuif_wr_en = {{cpuif.signal("PWRITE")}};
+assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
+assign cpuif_rd_en = !{{cpuif.signal("PWRITE")}};
+
 {%- for child in cpuif.addressable_children -%}
 {%- if child is array -%}
 for (genvar g_{{child.inst_name|lower}}_idx = 0; g_{{child.inst_name|lower}}_idx < N_{{child.inst_name|upper}}S; g_{{child.inst_name|lower}}_idx++) begin : g_passthrough_{{child.inst_name|lower}}
    assign {{self.signal("PCLK", child, f"g_{child.inst_name.lower()}_idx")}}    = {{self.signal("PCLK")}};
    assign {{self.signal("PRESETn", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PRESETn")}};
+    assign {{self.signal("PSELx", child, f"g_{child.inst_name.lower()}_idx")}}    = (cpuif_wr_sel[{{loop.index}}] || cpuif_rd_sel[{{loop.index}}]) ? 1'b1 : 1'b0;
    assign {{self.signal("PENABLE", child, f"g_{child.inst_name.lower()}_idx")}} = {{self.signal("PENABLE")}};
-    assign {{self.signal("PWRITE", child, f"g_{child.inst_name.lower()}_idx")}}  = {{self.signal("PWRITE")}};
-    assign {{self.signal("PADDR", child, f"g_{child.inst_name.lower()}_idx")}}   = {{self.signal("PADDR")}} [{{child.addr_width - 1}}:0]; // FIXME: Check slicing
+    assign {{self.signal("PWRITE", child, f"g_{child.inst_name.lower()}_idx")}}  = (cpuif_wr_sel[{{loop.index}}]) ? 1'b1 : 1'b0;
+    assign {{self.signal("PADDR", child, f"g_{child.inst_name.lower()}_idx")}}   = {{cpuif.get_address_slice(cpuif_wr_addr, child)}};
    assign {{self.signal("PPROT", child, f"g_{child.inst_name.lower()}_idx")}}   = {{self.signal("PPROT")}};
-    assign {{self.signal("PWDATA", child, f"g_{child.inst_name.lower()}_idx")}}  = {{self.signal("PWDATA")}};
+    assign {{self.signal("PWDATA", child, f"g_{child.inst_name.lower()}_idx")}}  = cpuif_wr_data;
    assign {{self.signal("PSTRB", child, f"g_{child.inst_name.lower()}_idx")}}   = {{self.signal("PSTRB")}};
+    assign cpuif_rd_ack[loop.index] = {{cpuif.signal("PREADY", child)}};
+    assign cpuif_rd_data[loop.index] = {{cpuif.signal("PRDATA", child)}};
+    assign cpuif_rd_err[loop.index] = {{cpuif.signal("PSLVERR", child)}};
 end
 {%- else -%}
 assign {{self.signal("PCLK", child)}}    = {{self.signal("PCLK")}};
 assign {{self.signal("PRESETn", child)}} = {{self.signal("PRESETn")}};
+assign {{self.signal("PSELx", child)}}    = (cpuif_wr_sel[{{loop.index0}}] || cpuif_rd_sel[{{loop.index0}}]) ? 1'b1 : 1'b0;
 assign {{self.signal("PENABLE", child)}} = {{self.signal("PENABLE")}};
-assign {{self.signal("PWRITE", child)}}  = {{self.signal("PWRITE")}};
-assign {{self.signal("PADDR", child)}}   = {{self.signal("PADDR")}} [{{child.addr_width - 1}}:0]; // FIXME: Check slicing
+assign {{self.signal("PWRITE", child)}}  = cpuif_wr_sel[{{loop.index}}] ? 1'b1 : 1'b0;
+assign {{self.signal("PADDR", child)}}   = {{cpuif.get_address_slice(cpuif_wr_addr, child)}};
 assign {{self.signal("PPROT", child)}}   = {{self.signal("PPROT")}};
-assign {{self.signal("PWDATA", child)}}  = {{self.signal("PWDATA")}};
+assign {{self.signal("PWDATA", child)}}  = cpuif_wr_data;
 assign {{self.signal("PSTRB", child)}}   = {{self.signal("PSTRB")}};
+assign cpuif_rd_ack[loop.index] = {{cpuif.signal("PREADY", child)}};
+assign cpuif_rd_data[loop.index] = {{cpuif.signal("PRDATA", child)}};
+assign cpuif_rd_err[loop.index] = {{cpuif.signal("PSLVERR", child)}};
 {%- endif -%}
 {%- endfor -%}

-//======================================================
-// Address Decode Logic
-//======================================================
 always_comb begin
-    // Default all PSELx signals to 0
-{%- for child in cpuif.addressable_children -%}
-{%- if child is array -%}
-    for (int {{child.inst_name|lower}}_idx = 0; {{child.inst_name|lower}}_idx < N_{{child.inst_name|upper}}S; {{child.inst_name|lower}}_idx++) begin
-        {{self.signal("PSELx", child, f"{child.inst_name.lower()}_idx")}} = 1'b0;
-    end
-{%- else -%}
-    {{self.signal("PSELx", child)}} = 1'b0;
-{%- endif -%}
-{%- endfor -%}
+    {{cpuif.signal("PREADY")}} = 1'b0;
+    {{cpuif.signal("PRDATA")}} = '0;
+    {{cpuif.signal("PSLVERR")}} = 1'b0;

-    if ({{self.signal("PSELx")}}) begin
-{%- for child in cpuif.addressable_children -%}
-{%- if loop.first -%}
-        if ({{cpuif.get_address_decode_condition(child)}}) begin
-{%- else -%}
-        end else if ({{cpuif.get_address_decode_condition(child)}}) begin
-{%- endif -%}
-            // Address matched for {{child.inst_name}} 
-{%- if child is array -%}
-            for (genvar {{child.inst_name|lower}}_idx = 0; {{child.inst_name|lower}}_idx < N_{{child.inst_name|upper}}S; {{child.inst_name|lower}}_idx++) begin
-                {{self.signal("PSELx", child, f"{child.inst_name.lower()}_idx")}} = 1'b1;
-            end
-{%- else -%}
-            {{self.signal("PSELx", child)}} = 1'b1;
-{%- endif -%} 
-{%- if loop.last -%}
-        end else begin
-            // No address matched
-{%- endif -%}
-{%- endfor -%}
+    for(int i = 0; i < {{cpuif.addressable_children | length}}; i++) begin
+        if (cpuif_rd_sel[i]) begin
+            {{cpuif.signal("PREADY")}} = cpuif_rd_ack[i];
+            {{cpuif.signal("PRDATA")}} = cpuif_rd_data[i];
+            {{cpuif.signal("PSLVERR")}} = cpuif_rd_err[i];
        end
-    end else begin
-        // PSELx is low, nothing to do
-    end
-end
-
-//======================================================
-// Read Data Mux
-//======================================================
-always_comb begin
-    // Default read data to 0
-    {{self.signal("PRDATA")}} = '0;
-    {{self.signal("PREADY")}} = 1'b1;
-    {{self.signal("PSLVERR")}} = 1'b0;
-
-    if ({{self.signal("PSELx")}} && !{{self.signal("PWRITE")}} && {{self.signal("PENABLE")}}) begin
-{%- for child in cpuif.addressable_children -%}
-{%- if loop.first -%}
-        if ({{cpuif.get_address_decode_condition(child)}}) begin
-{%- else -%}
-        end else if ({{cpuif.get_address_decode_condition(child)}}) begin
-{%- endif -%}
-            // Address matched for {{child.inst_name}} 
-{%- if child is array -%}
-            for (genvar {{child.inst_name|lower}}_idx = 0; {{child.inst_name|lower}}_idx < N_{{child.inst_name|upper}}S; {{child.inst_name|lower}}_idx++) begin
-                {{self.signal("PRDATA")}} = {{self.signal("PRDATA", child, f"{child.inst_name.lower()}_idx")}};
-                {{self.signal("PREADY")}} = {{self.signal("PREADY", child, f"{child.inst_name.lower()}_idx")}};
-                {{self.signal("PSLVERR")}} = {{self.signal("PSLVERR", child, f"{child.inst_name.lower()}_idx")}};
-            end
-{%- else -%}
-            {{self.signal("PRDATA")}}  = {{self.signal("PRDATA", child)}};
-            {{self.signal("PREADY")}}  = {{self.signal("PREADY", child)}};
-            {{self.signal("PSLVERR")}} = {{self.signal("PSLVERR", child)}};
-{%- endif -%} 
-{%- if loop.last -%}
-        end else begin
-            // No address matched
-            {{self.signal("PRDATA")}} = {'hdeadbeef}[{{ds.data_width - 1}}:0]; // Indicate error on no match
-            {{self.signal("PSLVERR")}} = 1'b1; // Indicate error on no match
-        end
-{%- endif -%}
-{%- endfor -%}
-    end else begin
-        // Not a read transfer, nothing to do
    end
 end
--- a/src/peakrdl_busdecoder/cpuif/base_cpuif.py
+++ b/src/peakrdl_busdecoder/cpuif/base_cpuif.py
@@ -1,6 +1,6 @@
-from typing import TYPE_CHECKING
 import inspect
 import os
+from typing import TYPE_CHECKING

 import jinja2 as jj
 from systemrdl.node import AddressableNode