format + module update

2025-10-13 22:06:51 -07:00
parent 54a199ca9c
commit 066d9ca99e
12 changed files with 109 additions and 139 deletions
--- a/src/peakrdl_busdecoder/cpuif/base_cpuif.py
+++ b/src/peakrdl_busdecoder/cpuif/base_cpuif.py
@@ -1,6 +1,6 @@
-from typing import TYPE_CHECKING
 import inspect
 import os
+from typing import TYPE_CHECKING

 import jinja2 as jj
 from systemrdl.node import AddressableNode