bslathi19/PeakRDL-BusDecoder
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format + module update

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This commit is contained in:
Arnav Sacheti
2025-10-13 22:06:51 -07:00
parent 54a199ca9c
commit 066d9ca99e
12 changed files with 109 additions and 139 deletions
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9
src/peakrdl_busdecoder/validate_design.py
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@@ -1,13 +1,10 @@
from typing import TYPE_CHECKING
from systemrdl.walker import RDLListener, RDLWalker, WalkerAction
from systemrdl.node import AddressableNode, AddrmapNode, FieldNode, Node, RegfileNode, RegNode, SignalNode
from systemrdl.rdltypes import PropertyReference
from systemrdl.node import Node, RegNode, FieldNode, SignalNode, AddressableNode
from systemrdl.node import RegfileNode, AddrmapNode
from systemrdl.walker import RDLListener, RDLWalker, WalkerAction
from .utils import roundup_pow2, is_pow2
from .utils import ref_is_internal
from .utils import is_pow2, ref_is_internal, roundup_pow2
if TYPE_CHECKING:
from .exporter import BusDecoderExporter