bslathi19/PeakRDL-BusDecoder
1
0
Fork 0
Code Issues Actions Packages Projects Releases Wiki Activity

use fanin_wr and fanin_rd

Browse Source
This commit is contained in:
Byron Lathi
2026-02-03 23:06:07 -08:00
parent b2923f4c7b
commit 094d38ff92
2 changed files with 13 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/peakrdl_busdecoder/cpuif/taxi_apb/taxi_apb_cpuif.py
View File

@@ -53,7 +53,7 @@ class TaxiAPBCpuif(BaseCpuif):
return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items())) return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
def fanin(self, node: AddressableNode | None = None) -> str: def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
fanin: dict[str, str] = {} fanin: dict[str, str] = {}
if node is None: if node is None:
fanin["cpuif_rd_ack"] = "'0" fanin["cpuif_rd_ack"] = "'0"
@@ -73,18 +73,27 @@ class TaxiAPBCpuif(BaseCpuif):
# no user? # no user?
return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items())) return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
def readback(self, node: AddressableNode | None = None) -> str: def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
fanin: dict[str, str] = {} fanin: dict[str, str] = {}
if node is None: if node is None:
fanin["cpuif_rd_ack"] = "'0"
fanin["cpuif_rd_err"] = "'0"
fanin["cpuif_rd_data"] = "'0" fanin["cpuif_rd_data"] = "'0"
if error:
fanin["cpuif_rd_ack"] = "'1"
fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
else: else:
# Use intermediate signals for interface arrays to avoid # Use intermediate signals for interface arrays to avoid
# non-constant indexing of interface arrays in procedural blocks # non-constant indexing of interface arrays in procedural blocks
if self.is_interface and node.is_array and node.array_dimensions: if self.is_interface and node.is_array and node.array_dimensions:
# Generate array index string [i0][i1]... for the intermediate signal # Generate array index string [i0][i1]... for the intermediate signal
array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions))) array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}" fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
else: else:
fanin["cpuif_rd_ack"] = self.signal("prdata", node, "i")
fanin["cpuif_rd_err"] = self.signal("pslverr", node, "i")
fanin["cpuif_rd_data"] = self.signal("prdata", node, "i") fanin["cpuif_rd_data"] = self.signal("prdata", node, "i")
return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items())) return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))

5
src/peakrdl_busdecoder/cpuif/taxi_apb/taxi_apb_tmpl.sv
View File

@@ -24,9 +24,8 @@ assign cpuif_wr_data = {{cpuif.signal("pwdata")}};
assign cpuif_wr_byte_en = {{cpuif.signal("pstrb")}}; assign cpuif_wr_byte_en = {{cpuif.signal("pstrb")}};
assign {{cpuif.signal("prdata")}} = cpuif_rd_data; assign {{cpuif.signal("prdata")}} = cpuif_rd_data;
assign {{cpuif.signal("pready")}} = cpuif_rd_ack; assign {{cpuif.signal("pready")}} = cpuif_rd_ack | cpuif_wr_ack;
assign {{cpuif.signal("pslverr")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err; assign {{cpuif.signal("pslverr")}} = cpuif_rd_err | cpuif_wr_err;
//-------------------------------------------------------------------------- //--------------------------------------------------------------------------
// Fanout CPU Bus interface signals // Fanout CPU Bus interface signals
//-------------------------------------------------------------------------- //--------------------------------------------------------------------------