adding decoder logic

src/peakrdl_busdecoder/cpuif/base_cpuif.py

@@ -82,6 +82,7 @@ class BaseCpuif:
         jj_env.filters["clog2"] = clog2  # type: ignore
         jj_env.filters["is_pow2"] = is_pow2  # type: ignore
         jj_env.filters["roundup_pow2"] = roundup_pow2  # type: ignore
+        jj_env.filters["address_slice"] = self.get_address_slice  # type: ignore
 
         context = {
             "cpuif": self,
@@ -90,3 +91,34 @@ class BaseCpuif:
 
         template = jj_env.get_template(self.template_path)
         return template.render(context)
+
+    def get_address_slice(self, node: AddressableNode) -> str:
+        """
+        Returns a SystemVerilog expression that extracts the address bits
+        relevant to the given node.
+        """
+        addr_mask = (1 << self.addr_width) - 1
+        addr = node.absolute_address & addr_mask
+        size = node.size
+        if size == 0:
+            raise ValueError(f"Node size '{size:#X}' must be greater than 0")
+        if (addr % size) != 0:
+            raise ValueError(f"Node address '{addr:#X}' must be aligned to its size '{size:#X}'")
+
+        # Calculate the address range of the node
+        addr_start = addr
+        addr_end = addr + size - 1
+        if addr_end > addr_mask:
+            raise ValueError("Node address range exceeds address width")
+
+        # Calculate the number of bits needed to represent the size
+        size_bits = size.bit_length() - 1
+        if size_bits < 0:
+            size_bits = 0
+
+        if size_bits >= self.addr_width:
+            # Node covers entire address space, so return full address
+            return ""
+
+        # Extract the relevant bits from PADDR
+        return f"[{self.addr_width - 1}:{size_bits}]"