adding decoder logic

2025-10-16 22:35:36 -07:00
parent 2937624ee7
commit 0c66453ba0
19 changed files with 354 additions and 326 deletions
--- a/src/peakrdl_busdecoder/module_tmpl.sv
+++ b/src/peakrdl_busdecoder/module_tmpl.sv
@@ -12,11 +12,11 @@


 module {{ds.module_name}}
-    {%- if cpuif.parameters %} #(
-        {{-cpuif.parameters|join(",\n")|indent(8)}}
-    ) {%- endif %} (
-        {{-cpuif.port_declaration|indent(8)}}
-    );
+{%- if cpuif.parameters %} #(
+    {{cpuif.parameters|join(",\n")|indent(4)}}
+) {%- endif %} (
+    {{cpuif.port_declaration|indent(4)}}
+);

    //--------------------------------------------------------------------------
    // CPU Bus interface logic