bslathi19/PeakRDL-BusDecoder
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Downsize paddr bits

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This commit is contained in:
Byron Lathi
2025-11-22 12:07:27 -08:00
parent 35d66db1b8
commit 217ff15431
2 changed files with 4 additions and 3 deletions
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4
src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py
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@@ -2,7 +2,7 @@ from typing import TYPE_CHECKING
from systemrdl.node import AddressableNode from systemrdl.node import AddressableNode
from ...utils import get_indexed_path from ...utils import clog2, get_indexed_path
from ..base_cpuif import BaseCpuif from ..base_cpuif import BaseCpuif
from .apb4_interface import APB4FlatInterface from .apb4_interface import APB4FlatInterface
@@ -42,7 +42,7 @@ class APB4CpuifFlat(BaseCpuif):
fanout[self.signal("PWRITE", node, "gi")] = ( fanout[self.signal("PWRITE", node, "gi")] = (
f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}" f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
) )
fanout[self.signal("PADDR", node, "gi")] = self.signal("PADDR") fanout[self.signal("PADDR", node, "gi")] = f"{self.signal('PADDR')}[{clog2(node.size) - 1}:0]"
fanout[self.signal("PPROT", node, "gi")] = self.signal("PPROT") fanout[self.signal("PPROT", node, "gi")] = self.signal("PPROT")
fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data" fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
fanout[self.signal("PSTRB", node, "gi")] = "cpuif_wr_byte_en" fanout[self.signal("PSTRB", node, "gi")] = "cpuif_wr_byte_en"

3
src/peakrdl_busdecoder/cpuif/apb4/apb4_interface.py
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@@ -2,6 +2,7 @@
from systemrdl.node import AddressableNode from systemrdl.node import AddressableNode
from ...utils import clog2
from ..interface import FlatInterface, SVInterface from ..interface import FlatInterface, SVInterface
@@ -50,7 +51,7 @@ class APB4FlatInterface(FlatInterface):
f"output logic {self.signal('PSEL', child)}", f"output logic {self.signal('PSEL', child)}",
f"output logic {self.signal('PENABLE', child)}", f"output logic {self.signal('PENABLE', child)}",
f"output logic {self.signal('PWRITE', child)}", f"output logic {self.signal('PWRITE', child)}",
f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('PADDR', child)}", f"output logic [{clog2(child.size) - 1}:0] {self.signal('PADDR', child)}",
f"output logic [2:0] {self.signal('PPROT', child)}", f"output logic [2:0] {self.signal('PPROT', child)}",
f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('PWDATA', child)}", f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('PWDATA', child)}",
f"output logic [{self.cpuif.data_width // 8 - 1}:0] {self.signal('PSTRB', child)}", f"output logic [{self.cpuif.data_width // 8 - 1}:0] {self.signal('PSTRB', child)}",