revamp docs

docs/index.rst

@@ -1,28 +1,34 @@
 Introduction
 ============
 
-PeakRDL-BusDecoder is a free and open-source bus decoder generator for hierarchical register address maps.
-This code generator translates your SystemRDL register description into a synthesizable 
-SystemVerilog RTL module that decodes CPU interface transactions and routes them to 
-multiple sub-address spaces (child addrmaps). This is particularly useful for:
+PeakRDL-BusDecoder is a free and open-source bus decoder generator for hierarchical
+SystemRDL address maps. It produces a synthesizable SystemVerilog RTL module that
+accepts a single CPU interface (slave side) and fans transactions out to multiple
+child address spaces (master side).
+
+This tool **does not** generate register storage or field logic. It is strictly a
+bus-routing layer that decodes addresses and forwards requests to child blocks.
+
+This is particularly useful for:
 
 * Creating hierarchical register maps with multiple sub-components
 * Splitting a single CPU interface bus to serve multiple independent register blocks
-* Organizing large register designs into logical sub-address spaces
+* Organizing large address spaces into logical sub-regions
 * Implementing address decode logic for multi-drop bus architectures
 
 The generated bus decoder provides:
 
 * Fully synthesizable SystemVerilog RTL (IEEE 1800-2012)
-* Support for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
+* A top-level slave CPU interface and per-child master CPU interfaces
 * Address decode logic that routes transactions to child address maps
-* Configurable pipelining options for designs with fast clock rates
-* Broad support for SystemRDL 2.0 features
+* Support for APB3, APB4, and AXI4-Lite (plus plugin-defined CPU interfaces)
+* Configurable decode depth and array unrolling
 
 
 Quick Start
 -----------
-The easiest way to use PeakRDL-BusDecoder is via the  `PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_:
+The easiest way to use PeakRDL-BusDecoder is via the
+`PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_:
 
 .. code-block:: bash
 
@@ -32,6 +38,20 @@ The easiest way to use PeakRDL-BusDecoder is via the  `PeakRDL command line tool
     # Export!
     peakrdl busdecoder atxmega_spi.rdl -o busdecoder/ --cpuif axi4-lite
 
+The exporter writes two files:
+
+* A SystemVerilog module (the bus decoder)
+* A SystemVerilog package (constants like data width and per-child address widths)
+
+Key command-line options:
+
+* ``--cpuif``: Select the CPU interface (``apb3``, ``apb3-flat``, ``apb4``, ``apb4-flat``, ``axi4-lite``, ``axi4-lite-flat``)
+* ``--module-name``: Override the generated module name
+* ``--package-name``: Override the generated package name
+* ``--addr-width``: Override the slave address width
+* ``--unroll``: Unroll arrayed children into discrete interfaces
+* ``--max-decode-depth``: Control how far the decoder descends into hierarchy
+
 
 Looking for VHDL?
 -----------------
@@ -55,10 +75,8 @@ Links
 
     self
     architecture
-    hwif
     configuring
     limitations
-    faq
     licensing
     api
 
@@ -69,29 +87,5 @@ Links
     cpuif/introduction
     cpuif/apb
     cpuif/axi4lite
-    cpuif/avalon
-    cpuif/passthrough
     cpuif/internal_protocol
     cpuif/customizing
-
-.. toctree::
-    :hidden:
-    :caption: SystemRDL Properties
-
-    props/field
-    props/reg
-    props/addrmap
-    props/signal
-    props/rhs_props
-
-.. toctree::
-    :hidden:
-    :caption: Other SystemRDL Features
-
-    rdl_features/external
-
-.. toctree::
-    :hidden:
-    :caption: Extended Properties
-
-    udps/intro