fix links

src/peakrdl_busdecoder/module_tmpl.sv

@@ -7,7 +7,7 @@
 //  Date: {{current_date}}
 //  Version: {{version}}
 //  Links:
-//    - https://github.com/SystemRDL/PeakRDL-busdecoder
+//    - https://github.com/arnavsacheti/PeakRDL-busdecoder
 //==========================================================
 
 

src/peakrdl_busdecoder/package_tmpl.sv

@@ -1,5 +1,5 @@
 // Generated by PeakRDL-busdecoder - A free and open-source SystemVerilog generator
-//  https://github.com/SystemRDL/PeakRDL-busdecoder
+//  https://github.com/arnavsacheti/PeakRDL-busdecoder
 
 package {{ds.package_name}};