fix cocotb units deprecation
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@@ -89,7 +89,7 @@ async def test_depth_1(dut):
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inner1.RDATA.value = 0
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inner1.RRESP.value = 0
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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# Write to address 0x0 (should select inner1)
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inner1.AWREADY.value = 1
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@@ -100,7 +100,7 @@ async def test_depth_1(dut):
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s_axil.WDATA.value = 0x12345678
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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assert int(inner1.AWVALID.value) == 1, "inner1 write address valid must be set"
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assert int(inner1.WVALID.value) == 1, "inner1 write data valid must be set"
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@@ -138,7 +138,7 @@ async def test_depth_2(dut):
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master.RDATA.value = 0
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master.RRESP.value = 0
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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# Write to address 0x0 (should select reg1)
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reg1.AWREADY.value = 1
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@@ -149,7 +149,7 @@ async def test_depth_2(dut):
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s_axil.WDATA.value = 0xABCDEF01
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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assert int(reg1.AWVALID.value) == 1, "reg1 must be selected for address 0x0"
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assert int(inner2.AWVALID.value) == 0, "inner2 should not be selected"
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@@ -159,7 +159,7 @@ async def test_depth_2(dut):
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s_axil.WVALID.value = 0
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reg1.AWREADY.value = 0
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reg1.WREADY.value = 0
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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# Write to address 0x10 (should select inner2)
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inner2.AWREADY.value = 1
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@@ -170,7 +170,7 @@ async def test_depth_2(dut):
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s_axil.WDATA.value = 0x23456789
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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assert int(inner2.AWVALID.value) == 1, "inner2 must be selected for address 0x10"
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assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"
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@@ -209,7 +209,7 @@ async def test_depth_0(dut):
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master.RDATA.value = 0
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master.RRESP.value = 0
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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# Write to address 0x0 (should select reg1)
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reg1.AWREADY.value = 1
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@@ -220,7 +220,7 @@ async def test_depth_0(dut):
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s_axil.WDATA.value = 0x11111111
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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assert int(reg1.AWVALID.value) == 1, "reg1 must be selected for address 0x0"
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assert int(reg2.AWVALID.value) == 0, "reg2 should not be selected"
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@@ -231,7 +231,7 @@ async def test_depth_0(dut):
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s_axil.WVALID.value = 0
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reg1.AWREADY.value = 0
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reg1.WREADY.value = 0
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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# Write to address 0x10 (should select reg2)
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reg2.AWREADY.value = 1
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@@ -242,7 +242,7 @@ async def test_depth_0(dut):
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s_axil.WDATA.value = 0x22222222
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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assert int(reg2.AWVALID.value) == 1, "reg2 must be selected for address 0x10"
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assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"
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@@ -253,7 +253,7 @@ async def test_depth_0(dut):
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s_axil.WVALID.value = 0
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reg2.AWREADY.value = 0
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reg2.WREADY.value = 0
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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# Write to address 0x14 (should select reg2b)
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reg2b.AWREADY.value = 1
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@@ -264,7 +264,7 @@ async def test_depth_0(dut):
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s_axil.WDATA.value = 0x33333333
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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await Timer(1, unit="ns")
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assert int(reg2b.AWVALID.value) == 1, "reg2b must be selected for address 0x14"
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assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"
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