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fix cocotb units deprecation

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This commit is contained in:
Arnav Sacheti
2026-02-03 05:41:48 +00:00
parent caad523b06
commit 2abf7cf7f2
6 changed files with 51 additions and 51 deletions
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10
tests/cocotb/apb3/smoke/test_register_access.py
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@@ -106,7 +106,7 @@ async def test_apb3_address_decoding(dut) -> None:
_set_value(entry["inputs"]["PREADY"], idx, 0) _set_value(entry["inputs"]["PREADY"], idx, 0)
_set_value(entry["inputs"]["PSLVERR"], idx, 0) _set_value(entry["inputs"]["PSLVERR"], idx, 0)
await Timer(1, units="ns") await Timer(1, unit="ns")
addr_mask = (1 << config["address_width"]) - 1 addr_mask = (1 << config["address_width"]) - 1
@@ -132,7 +132,7 @@ async def test_apb3_address_decoding(dut) -> None:
) )
master_address = (address - entry["inst_address"]) % entry["inst_size"] master_address = (address - entry["inst_address"]) % entry["inst_size"]
await Timer(1, units="ns") await Timer(1, unit="ns")
assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write" assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write direction" assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write direction"
@@ -158,7 +158,7 @@ async def test_apb3_address_decoding(dut) -> None:
slave.PENABLE.value = 0 slave.PENABLE.value = 0
slave.PWRITE.value = 0 slave.PWRITE.value = 0
_set_value(entry["inputs"]["PREADY"], index, 0) _set_value(entry["inputs"]["PREADY"], index, 0)
await Timer(1, units="ns") await Timer(1, unit="ns")
# ------------------------------------------------------------------ # ------------------------------------------------------------------
# Read phase # Read phase
@@ -173,7 +173,7 @@ async def test_apb3_address_decoding(dut) -> None:
slave.PSEL.value = 1 slave.PSEL.value = 1
slave.PENABLE.value = 1 slave.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must assert PSEL for read" assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must assert PSEL for read"
assert _get_int(entry["outputs"]["PWRITE"], index) == 0, ( assert _get_int(entry["outputs"]["PWRITE"], index) == 0, (
@@ -199,4 +199,4 @@ async def test_apb3_address_decoding(dut) -> None:
slave.PENABLE.value = 0 slave.PENABLE.value = 0
_set_value(entry["inputs"]["PREADY"], index, 0) _set_value(entry["inputs"]["PREADY"], index, 0)
_set_value(entry["inputs"]["PRDATA"], index, 0) _set_value(entry["inputs"]["PRDATA"], index, 0)
await Timer(1, units="ns") await Timer(1, unit="ns")

24
tests/cocotb/apb3/smoke/test_variable_depth.py
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@@ -56,7 +56,7 @@ async def test_depth_1(dut):
inner1.PREADY.value = 0 inner1.PREADY.value = 0
inner1.PSLVERR.value = 0 inner1.PSLVERR.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x0 (should select inner1) # Write to address 0x0 (should select inner1)
inner1.PREADY.value = 1 inner1.PREADY.value = 1
@@ -66,7 +66,7 @@ async def test_depth_1(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(inner1.PSEL.value) == 1, "inner1 must be selected" assert int(inner1.PSEL.value) == 1, "inner1 must be selected"
assert int(inner1.PWRITE.value) == 1, "Write should propagate" assert int(inner1.PWRITE.value) == 1, "Write should propagate"
@@ -97,7 +97,7 @@ async def test_depth_2(dut):
inner2.PREADY.value = 0 inner2.PREADY.value = 0
inner2.PSLVERR.value = 0 inner2.PSLVERR.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x0 (should select reg1) # Write to address 0x0 (should select reg1)
reg1.PREADY.value = 1 reg1.PREADY.value = 1
@@ -107,7 +107,7 @@ async def test_depth_2(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0" assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0"
assert int(inner2.PSEL.value) == 0, "inner2 should not be selected" assert int(inner2.PSEL.value) == 0, "inner2 should not be selected"
@@ -116,7 +116,7 @@ async def test_depth_2(dut):
s_apb.PSEL.value = 0 s_apb.PSEL.value = 0
s_apb.PENABLE.value = 0 s_apb.PENABLE.value = 0
reg1.PREADY.value = 0 reg1.PREADY.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x10 (should select inner2) # Write to address 0x10 (should select inner2)
inner2.PREADY.value = 1 inner2.PREADY.value = 1
@@ -126,7 +126,7 @@ async def test_depth_2(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(inner2.PSEL.value) == 1, "inner2 must be selected for address 0x10" assert int(inner2.PSEL.value) == 1, "inner2 must be selected for address 0x10"
assert int(reg1.PSEL.value) == 0, "reg1 should not be selected" assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"
@@ -154,7 +154,7 @@ async def test_depth_0(dut):
master.PREADY.value = 0 master.PREADY.value = 0
master.PSLVERR.value = 0 master.PSLVERR.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x0 (should select reg1) # Write to address 0x0 (should select reg1)
reg1.PREADY.value = 1 reg1.PREADY.value = 1
@@ -164,7 +164,7 @@ async def test_depth_0(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0" assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0"
assert int(reg2.PSEL.value) == 0, "reg2 should not be selected" assert int(reg2.PSEL.value) == 0, "reg2 should not be selected"
@@ -174,7 +174,7 @@ async def test_depth_0(dut):
s_apb.PSEL.value = 0 s_apb.PSEL.value = 0
s_apb.PENABLE.value = 0 s_apb.PENABLE.value = 0
reg1.PREADY.value = 0 reg1.PREADY.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x10 (should select reg2) # Write to address 0x10 (should select reg2)
reg2.PREADY.value = 1 reg2.PREADY.value = 1
@@ -184,7 +184,7 @@ async def test_depth_0(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg2.PSEL.value) == 1, "reg2 must be selected for address 0x10" assert int(reg2.PSEL.value) == 1, "reg2 must be selected for address 0x10"
assert int(reg1.PSEL.value) == 0, "reg1 should not be selected" assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"
@@ -194,7 +194,7 @@ async def test_depth_0(dut):
s_apb.PSEL.value = 0 s_apb.PSEL.value = 0
s_apb.PENABLE.value = 0 s_apb.PENABLE.value = 0
reg2.PREADY.value = 0 reg2.PREADY.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x14 (should select reg2b) # Write to address 0x14 (should select reg2b)
reg2b.PREADY.value = 1 reg2b.PREADY.value = 1
@@ -204,7 +204,7 @@ async def test_depth_0(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg2b.PSEL.value) == 1, "reg2b must be selected for address 0x14" assert int(reg2b.PSEL.value) == 1, "reg2b must be selected for address 0x14"
assert int(reg1.PSEL.value) == 0, "reg1 should not be selected" assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"

10
tests/cocotb/apb4/smoke/test_register_access.py
View File

@@ -116,7 +116,7 @@ async def test_apb4_address_decoding(dut) -> None:
_set_value(entry["inputs"]["PREADY"], idx, 0) _set_value(entry["inputs"]["PREADY"], idx, 0)
_set_value(entry["inputs"]["PSLVERR"], idx, 0) _set_value(entry["inputs"]["PSLVERR"], idx, 0)
await Timer(1, units="ns") await Timer(1, unit="ns")
addr_mask = (1 << config["address_width"]) - 1 addr_mask = (1 << config["address_width"]) - 1
strobe_mask = (1 << config["byte_width"]) - 1 strobe_mask = (1 << config["byte_width"]) - 1
@@ -146,7 +146,7 @@ async def test_apb4_address_decoding(dut) -> None:
) )
master_address = (address - entry["inst_address"]) % entry["inst_size"] master_address = (address - entry["inst_address"]) % entry["inst_size"]
await Timer(1, units="ns") await Timer(1, unit="ns")
assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write" assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write intent" assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write intent"
@@ -176,7 +176,7 @@ async def test_apb4_address_decoding(dut) -> None:
slave.PENABLE.value = 0 slave.PENABLE.value = 0
slave.PWRITE.value = 0 slave.PWRITE.value = 0
_set_value(entry["inputs"]["PREADY"], index, 0) _set_value(entry["inputs"]["PREADY"], index, 0)
await Timer(1, units="ns") await Timer(1, unit="ns")
# ------------------------------------------------------------------ # ------------------------------------------------------------------
# Read phase # Read phase
@@ -191,7 +191,7 @@ async def test_apb4_address_decoding(dut) -> None:
slave.PSEL.value = 1 slave.PSEL.value = 1
slave.PENABLE.value = 1 slave.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must assert PSEL for read" assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must assert PSEL for read"
assert _get_int(entry["outputs"]["PWRITE"], index) == 0, ( assert _get_int(entry["outputs"]["PWRITE"], index) == 0, (
@@ -218,4 +218,4 @@ async def test_apb4_address_decoding(dut) -> None:
slave.PENABLE.value = 0 slave.PENABLE.value = 0
_set_value(entry["inputs"]["PREADY"], index, 0) _set_value(entry["inputs"]["PREADY"], index, 0)
_set_value(entry["inputs"]["PRDATA"], index, 0) _set_value(entry["inputs"]["PRDATA"], index, 0)
await Timer(1, units="ns") await Timer(1, unit="ns")

24
tests/cocotb/apb4/smoke/test_variable_depth.py
View File

@@ -62,7 +62,7 @@ async def test_depth_1(dut):
inner1.PREADY.value = 0 inner1.PREADY.value = 0
inner1.PSLVERR.value = 0 inner1.PSLVERR.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x0 (should select inner1) # Write to address 0x0 (should select inner1)
inner1.PREADY.value = 1 inner1.PREADY.value = 1
@@ -73,7 +73,7 @@ async def test_depth_1(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(inner1.PSEL.value) == 1, "inner1 must be selected" assert int(inner1.PSEL.value) == 1, "inner1 must be selected"
assert int(inner1.PWRITE.value) == 1, "Write should propagate" assert int(inner1.PWRITE.value) == 1, "Write should propagate"
@@ -106,7 +106,7 @@ async def test_depth_2(dut):
inner2.PREADY.value = 0 inner2.PREADY.value = 0
inner2.PSLVERR.value = 0 inner2.PSLVERR.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x0 (should select reg1) # Write to address 0x0 (should select reg1)
reg1.PREADY.value = 1 reg1.PREADY.value = 1
@@ -117,7 +117,7 @@ async def test_depth_2(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0" assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0"
assert int(inner2.PSEL.value) == 0, "inner2 should not be selected" assert int(inner2.PSEL.value) == 0, "inner2 should not be selected"
@@ -126,7 +126,7 @@ async def test_depth_2(dut):
s_apb.PSEL.value = 0 s_apb.PSEL.value = 0
s_apb.PENABLE.value = 0 s_apb.PENABLE.value = 0
reg1.PREADY.value = 0 reg1.PREADY.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x10 (should select inner2) # Write to address 0x10 (should select inner2)
inner2.PREADY.value = 1 inner2.PREADY.value = 1
@@ -137,7 +137,7 @@ async def test_depth_2(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(inner2.PSEL.value) == 1, "inner2 must be selected for address 0x10" assert int(inner2.PSEL.value) == 1, "inner2 must be selected for address 0x10"
assert int(reg1.PSEL.value) == 0, "reg1 should not be selected" assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"
@@ -167,7 +167,7 @@ async def test_depth_0(dut):
master.PREADY.value = 0 master.PREADY.value = 0
master.PSLVERR.value = 0 master.PSLVERR.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x0 (should select reg1) # Write to address 0x0 (should select reg1)
reg1.PREADY.value = 1 reg1.PREADY.value = 1
@@ -178,7 +178,7 @@ async def test_depth_0(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0" assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0"
assert int(reg2.PSEL.value) == 0, "reg2 should not be selected" assert int(reg2.PSEL.value) == 0, "reg2 should not be selected"
@@ -188,7 +188,7 @@ async def test_depth_0(dut):
s_apb.PSEL.value = 0 s_apb.PSEL.value = 0
s_apb.PENABLE.value = 0 s_apb.PENABLE.value = 0
reg1.PREADY.value = 0 reg1.PREADY.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x10 (should select reg2) # Write to address 0x10 (should select reg2)
reg2.PREADY.value = 1 reg2.PREADY.value = 1
@@ -199,7 +199,7 @@ async def test_depth_0(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg2.PSEL.value) == 1, "reg2 must be selected for address 0x10" assert int(reg2.PSEL.value) == 1, "reg2 must be selected for address 0x10"
assert int(reg1.PSEL.value) == 0, "reg1 should not be selected" assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"
@@ -209,7 +209,7 @@ async def test_depth_0(dut):
s_apb.PSEL.value = 0 s_apb.PSEL.value = 0
s_apb.PENABLE.value = 0 s_apb.PENABLE.value = 0
reg2.PREADY.value = 0 reg2.PREADY.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x14 (should select reg2b) # Write to address 0x14 (should select reg2b)
reg2b.PREADY.value = 1 reg2b.PREADY.value = 1
@@ -220,7 +220,7 @@ async def test_depth_0(dut):
s_apb.PSEL.value = 1 s_apb.PSEL.value = 1
s_apb.PENABLE.value = 1 s_apb.PENABLE.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg2b.PSEL.value) == 1, "reg2b must be selected for address 0x14" assert int(reg2b.PSEL.value) == 1, "reg2b must be selected for address 0x14"
assert int(reg1.PSEL.value) == 0, "reg1 should not be selected" assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"

10
tests/cocotb/axi4lite/smoke/test_register_access.py
View File

@@ -137,7 +137,7 @@ async def test_axi4lite_address_decoding(dut) -> None:
_set_value(entry["inputs"]["RDATA"], idx, 0) _set_value(entry["inputs"]["RDATA"], idx, 0)
_set_value(entry["inputs"]["RRESP"], idx, 0) _set_value(entry["inputs"]["RRESP"], idx, 0)
await Timer(1, units="ns") await Timer(1, unit="ns")
addr_mask = (1 << config["address_width"]) - 1 addr_mask = (1 << config["address_width"]) - 1
strobe_mask = (1 << config["byte_width"]) - 1 strobe_mask = (1 << config["byte_width"]) - 1
@@ -163,7 +163,7 @@ async def test_axi4lite_address_decoding(dut) -> None:
) )
master_address = (address - entry["inst_address"]) % entry["inst_size"] master_address = (address - entry["inst_address"]) % entry["inst_size"]
await Timer(1, units="ns") await Timer(1, unit="ns")
assert _get_int(entry["outputs"]["AWVALID"], index) == 1, f"{master_name} should see AWVALID asserted" assert _get_int(entry["outputs"]["AWVALID"], index) == 1, f"{master_name} should see AWVALID asserted"
assert _get_int(entry["outputs"]["AWADDR"], index) == master_address, ( assert _get_int(entry["outputs"]["AWADDR"], index) == master_address, (
@@ -187,7 +187,7 @@ async def test_axi4lite_address_decoding(dut) -> None:
slave.AWVALID.value = 0 slave.AWVALID.value = 0
slave.WVALID.value = 0 slave.WVALID.value = 0
slave.BREADY.value = 0 slave.BREADY.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
read_data = _read_pattern(address, config["data_width"]) read_data = _read_pattern(address, config["data_width"])
_set_value(entry["inputs"]["RVALID"], index, 1) _set_value(entry["inputs"]["RVALID"], index, 1)
@@ -199,7 +199,7 @@ async def test_axi4lite_address_decoding(dut) -> None:
slave.ARVALID.value = 1 slave.ARVALID.value = 1
slave.RREADY.value = 1 slave.RREADY.value = 1
await Timer(1, units="ns") await Timer(1, unit="ns")
assert _get_int(entry["outputs"]["ARVALID"], index) == 1, f"{master_name} should assert ARVALID" assert _get_int(entry["outputs"]["ARVALID"], index) == 1, f"{master_name} should assert ARVALID"
assert _get_int(entry["outputs"]["ARADDR"], index) == master_address, ( assert _get_int(entry["outputs"]["ARADDR"], index) == master_address, (
@@ -222,4 +222,4 @@ async def test_axi4lite_address_decoding(dut) -> None:
slave.RREADY.value = 0 slave.RREADY.value = 0
_set_value(entry["inputs"]["RVALID"], index, 0) _set_value(entry["inputs"]["RVALID"], index, 0)
_set_value(entry["inputs"]["RDATA"], index, 0) _set_value(entry["inputs"]["RDATA"], index, 0)
await Timer(1, units="ns") await Timer(1, unit="ns")

24
tests/cocotb/axi4lite/smoke/test_variable_depth.py
View File

@@ -89,7 +89,7 @@ async def test_depth_1(dut):
inner1.RDATA.value = 0 inner1.RDATA.value = 0
inner1.RRESP.value = 0 inner1.RRESP.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x0 (should select inner1) # Write to address 0x0 (should select inner1)
inner1.AWREADY.value = 1 inner1.AWREADY.value = 1
@@ -100,7 +100,7 @@ async def test_depth_1(dut):
s_axil.WDATA.value = 0x12345678 s_axil.WDATA.value = 0x12345678
s_axil.WSTRB.value = 0xF s_axil.WSTRB.value = 0xF
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(inner1.AWVALID.value) == 1, "inner1 write address valid must be set" assert int(inner1.AWVALID.value) == 1, "inner1 write address valid must be set"
assert int(inner1.WVALID.value) == 1, "inner1 write data valid must be set" assert int(inner1.WVALID.value) == 1, "inner1 write data valid must be set"
@@ -138,7 +138,7 @@ async def test_depth_2(dut):
master.RDATA.value = 0 master.RDATA.value = 0
master.RRESP.value = 0 master.RRESP.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x0 (should select reg1) # Write to address 0x0 (should select reg1)
reg1.AWREADY.value = 1 reg1.AWREADY.value = 1
@@ -149,7 +149,7 @@ async def test_depth_2(dut):
s_axil.WDATA.value = 0xABCDEF01 s_axil.WDATA.value = 0xABCDEF01
s_axil.WSTRB.value = 0xF s_axil.WSTRB.value = 0xF
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg1.AWVALID.value) == 1, "reg1 must be selected for address 0x0" assert int(reg1.AWVALID.value) == 1, "reg1 must be selected for address 0x0"
assert int(inner2.AWVALID.value) == 0, "inner2 should not be selected" assert int(inner2.AWVALID.value) == 0, "inner2 should not be selected"
@@ -159,7 +159,7 @@ async def test_depth_2(dut):
s_axil.WVALID.value = 0 s_axil.WVALID.value = 0
reg1.AWREADY.value = 0 reg1.AWREADY.value = 0
reg1.WREADY.value = 0 reg1.WREADY.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x10 (should select inner2) # Write to address 0x10 (should select inner2)
inner2.AWREADY.value = 1 inner2.AWREADY.value = 1
@@ -170,7 +170,7 @@ async def test_depth_2(dut):
s_axil.WDATA.value = 0x23456789 s_axil.WDATA.value = 0x23456789
s_axil.WSTRB.value = 0xF s_axil.WSTRB.value = 0xF
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(inner2.AWVALID.value) == 1, "inner2 must be selected for address 0x10" assert int(inner2.AWVALID.value) == 1, "inner2 must be selected for address 0x10"
assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected" assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"
@@ -209,7 +209,7 @@ async def test_depth_0(dut):
master.RDATA.value = 0 master.RDATA.value = 0
master.RRESP.value = 0 master.RRESP.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x0 (should select reg1) # Write to address 0x0 (should select reg1)
reg1.AWREADY.value = 1 reg1.AWREADY.value = 1
@@ -220,7 +220,7 @@ async def test_depth_0(dut):
s_axil.WDATA.value = 0x11111111 s_axil.WDATA.value = 0x11111111
s_axil.WSTRB.value = 0xF s_axil.WSTRB.value = 0xF
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg1.AWVALID.value) == 1, "reg1 must be selected for address 0x0" assert int(reg1.AWVALID.value) == 1, "reg1 must be selected for address 0x0"
assert int(reg2.AWVALID.value) == 0, "reg2 should not be selected" assert int(reg2.AWVALID.value) == 0, "reg2 should not be selected"
@@ -231,7 +231,7 @@ async def test_depth_0(dut):
s_axil.WVALID.value = 0 s_axil.WVALID.value = 0
reg1.AWREADY.value = 0 reg1.AWREADY.value = 0
reg1.WREADY.value = 0 reg1.WREADY.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x10 (should select reg2) # Write to address 0x10 (should select reg2)
reg2.AWREADY.value = 1 reg2.AWREADY.value = 1
@@ -242,7 +242,7 @@ async def test_depth_0(dut):
s_axil.WDATA.value = 0x22222222 s_axil.WDATA.value = 0x22222222
s_axil.WSTRB.value = 0xF s_axil.WSTRB.value = 0xF
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg2.AWVALID.value) == 1, "reg2 must be selected for address 0x10" assert int(reg2.AWVALID.value) == 1, "reg2 must be selected for address 0x10"
assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected" assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"
@@ -253,7 +253,7 @@ async def test_depth_0(dut):
s_axil.WVALID.value = 0 s_axil.WVALID.value = 0
reg2.AWREADY.value = 0 reg2.AWREADY.value = 0
reg2.WREADY.value = 0 reg2.WREADY.value = 0
await Timer(1, units="ns") await Timer(1, unit="ns")
# Write to address 0x14 (should select reg2b) # Write to address 0x14 (should select reg2b)
reg2b.AWREADY.value = 1 reg2b.AWREADY.value = 1
@@ -264,7 +264,7 @@ async def test_depth_0(dut):
s_axil.WDATA.value = 0x33333333 s_axil.WDATA.value = 0x33333333
s_axil.WSTRB.value = 0xF s_axil.WSTRB.value = 0xF
await Timer(1, units="ns") await Timer(1, unit="ns")
assert int(reg2b.AWVALID.value) == 1, "reg2b must be selected for address 0x14" assert int(reg2b.AWVALID.value) == 1, "reg2b must be selected for address 0x14"
assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected" assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"