Add comprehensive test suite for PeakRDL-BusDecoder with sub-block and integration tests (#6)
* Initial plan * Add comprehensive test suite for PeakRDL-BusDecoder - Added tests for utility functions (clog2, is_pow2, roundup_pow2, get_indexed_path) - Added tests for body classes (Body, ForLoopBody, IfBody, CombinationalBody, StructBody) - Added tests for code generators (DecodeLogicGenerator, StructGenerator) - Added tests for DesignState configuration - Added integration tests for BusDecoderExporter - Added tests for APB4 interface generation - Fixed conftest to properly handle RDLCompiler and temporary files - All 56 tests passing Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Format test files with ruff Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
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312
tests/unit/test_generators.py
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312
tests/unit/test_generators.py
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"""Tests for code generation classes."""
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from __future__ import annotations
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import pytest
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from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
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from peakrdl_busdecoder.decode_logic_gen import DecodeLogicFlavor, DecodeLogicGenerator
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from peakrdl_busdecoder.design_state import DesignState
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from peakrdl_busdecoder.exporter import BusDecoderExporter
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from peakrdl_busdecoder.struct_gen import StructGenerator
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class TestDecodeLogicGenerator:
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"""Test the DecodeLogicGenerator."""
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def test_decode_logic_read(self, compile_rdl):
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"""Test decode logic generation for read operations."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {})
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gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.READ)
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# Basic sanity check - it should initialize
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assert gen is not None
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assert gen._flavor == DecodeLogicFlavor.READ
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def test_decode_logic_write(self, compile_rdl):
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"""Test decode logic generation for write operations."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {})
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gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.WRITE)
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assert gen is not None
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assert gen._flavor == DecodeLogicFlavor.WRITE
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def test_cpuif_addr_predicate(self, compile_rdl):
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"""Test address predicate generation."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x100;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {})
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gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.READ)
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# Get the register node
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reg_node = None
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for child in top.children():
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if child.inst_name == "my_reg":
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reg_node = child
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break
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assert reg_node is not None
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predicates = gen.cpuif_addr_predicate(reg_node)
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# Should return a list of conditions
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assert isinstance(predicates, list)
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assert len(predicates) > 0
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# Should check address bounds
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for pred in predicates:
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assert "cpuif_rd_addr" in pred or ">=" in pred or "<" in pred
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def test_decode_logic_flavor_enum(self):
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"""Test DecodeLogicFlavor enum values."""
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assert DecodeLogicFlavor.READ.value == "rd"
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assert DecodeLogicFlavor.WRITE.value == "wr"
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assert DecodeLogicFlavor.READ.cpuif_address == "cpuif_rd_addr"
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assert DecodeLogicFlavor.WRITE.cpuif_address == "cpuif_wr_addr"
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assert DecodeLogicFlavor.READ.cpuif_select == "cpuif_rd_sel"
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assert DecodeLogicFlavor.WRITE.cpuif_select == "cpuif_wr_sel"
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class TestStructGenerator:
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"""Test the StructGenerator."""
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def test_simple_struct_generation(self, compile_rdl):
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"""Test struct generation for simple register."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {})
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gen = StructGenerator(ds)
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# Should generate struct definition
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assert gen is not None
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result = str(gen)
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# Should contain struct declaration
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assert "struct" in result or "typedef" in result
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def test_nested_struct_generation(self, compile_rdl):
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"""Test struct generation for nested addrmaps."""
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rdl_source = """
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addrmap inner {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} inner_reg @ 0x0;
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};
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addrmap outer {
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inner my_inner @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="outer")
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ds = DesignState(top, {})
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gen = StructGenerator(ds)
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# Walk the tree to generate structs
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from systemrdl.walker import RDLWalker
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walker = RDLWalker()
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walker.walk(top, gen, skip_top=True)
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result = str(gen)
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# Should contain struct declaration
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assert "struct" in result or "typedef" in result
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# The struct should reference the inner component
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assert "my_inner" in result
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def test_array_struct_generation(self, compile_rdl):
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"""Test struct generation for register arrays."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_regs[4] @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {})
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gen = StructGenerator(ds)
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# Walk the tree to generate structs
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from systemrdl.walker import RDLWalker
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walker = RDLWalker()
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walker.walk(top, gen, skip_top=True)
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result = str(gen)
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# Should contain array notation
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assert "[" in result and "]" in result
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# Should reference the register
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assert "my_regs" in result
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class TestDesignState:
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"""Test the DesignState class."""
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def test_design_state_basic(self, compile_rdl):
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"""Test basic DesignState initialization."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {})
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assert ds.top_node == top
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assert ds.module_name == "test"
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assert ds.package_name == "test_pkg"
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assert ds.cpuif_data_width == 32 # Should infer from 32-bit field
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assert ds.addr_width > 0
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def test_design_state_custom_module_name(self, compile_rdl):
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"""Test DesignState with custom module name."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {"module_name": "custom_module"})
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assert ds.module_name == "custom_module"
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assert ds.package_name == "custom_module_pkg"
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def test_design_state_custom_package_name(self, compile_rdl):
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"""Test DesignState with custom package name."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {"package_name": "custom_pkg"})
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assert ds.package_name == "custom_pkg"
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def test_design_state_custom_address_width(self, compile_rdl):
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"""Test DesignState with custom address width."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {"address_width": 16})
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assert ds.addr_width == 16
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def test_design_state_unroll_arrays(self, compile_rdl):
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"""Test DesignState with cpuif_unroll option."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_regs[4] @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {"cpuif_unroll": True})
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assert ds.cpuif_unroll is True
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def test_design_state_64bit_registers(self, compile_rdl):
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"""Test DesignState with wider data width."""
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rdl_source = """
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addrmap test {
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reg {
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regwidth = 32;
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {})
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# Should infer 32-bit data width from field
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assert ds.cpuif_data_width == 32
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