Add cocotb testbench for validating generated bus decoder RTL across APB3, APB4, and AXI4-Lite interfaces (#9)
* Initial plan * Add cocotb test infrastructure and testbenches for APB3, APB4, and AXI4-Lite Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add integration tests, examples, and documentation for cocotb testbenches Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Address code review feedback: use relative imports and update installation docs Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add implementation summary document Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Merge cocotb dependencies into test group Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add optional cocotb simulation workflow with Icarus Verilog Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
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tests/cocotb/IMPLEMENTATION_SUMMARY.md
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# Cocotb Testbench Implementation Summary
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## Overview
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This implementation adds comprehensive cocotb-based testbenches for validating generated SystemVerilog bus decoder RTL across multiple CPU interface types (APB3, APB4, and AXI4-Lite).
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## Files Added
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### Test Infrastructure
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- **pyproject.toml** - Added cocotb-test dependency group
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- **tests/cocotb/common/utils.py** - Utilities for RDL compilation and code generation
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- **tests/cocotb/common/apb4_master.py** - APB4 Bus Functional Model
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- **tests/cocotb/Makefile.common** - Makefile template for cocotb simulations
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### Testbenches
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- **tests/cocotb/testbenches/test_apb4_decoder.py** - APB4 interface tests (3 test cases)
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- test_simple_read_write: Basic read/write operations
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- test_multiple_registers: Multiple register access
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- test_byte_strobe: Byte strobe functionality
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- **tests/cocotb/testbenches/test_apb3_decoder.py** - APB3 interface tests (2 test cases)
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- test_simple_read_write: Basic read/write operations
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- test_multiple_registers: Multiple register access
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- **tests/cocotb/testbenches/test_axi4lite_decoder.py** - AXI4-Lite interface tests (3 test cases)
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- test_simple_read_write: Basic read/write operations
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- test_multiple_registers: Multiple register access
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- test_byte_strobe: Byte strobe functionality
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- **tests/cocotb/testbenches/test_apb4_runner.py** - Pytest wrapper for running APB4 tests
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- **tests/cocotb/testbenches/test_integration.py** - Integration tests (9 test cases)
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- Tests code generation for all three interfaces
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- Tests utility functions
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- Validates generated code structure
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### Documentation & Examples
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- **tests/cocotb/README.md** - Comprehensive cocotb test documentation
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- **tests/cocotb/examples.py** - Example script demonstrating code generation
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- **tests/README.md** - Updated with cocotb test instructions
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## Features
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### Bus Functional Models (BFMs)
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Each CPU interface has both master and slave BFMs:
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- **APB4Master/APB4SlaveResponder**: Full APB4 protocol with PSTRB support
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- **APB3Master/APB3SlaveResponder**: APB3 protocol without PSTRB
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- **AXI4LiteMaster/AXI4LiteSlaveResponder**: Full AXI4-Lite protocol with separate channels
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### Test Coverage
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1. **Simple read/write operations**: Verify basic decoder functionality
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2. **Multiple registers**: Test address decoding for multiple targets
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3. **Register arrays**: Validate array handling
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4. **Byte strobes**: Test partial word writes (APB4, AXI4-Lite)
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5. **Nested address maps**: Validate hierarchical structures
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### Code Generation Tests
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The integration tests validate:
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- Code generation for all three CPU interfaces
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- Custom module/package naming
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- Register arrays
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- Nested address maps
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- Generated code structure and content
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## How to Run
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### Integration Tests (No Simulator Required)
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```bash
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pytest tests/cocotb/testbenches/test_integration.py -v
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```
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### Example Script
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```bash
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python -m tests.cocotb.examples
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```
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### Full Simulation Tests (Requires Simulator)
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```bash
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# Install simulator first
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apt-get install iverilog # or verilator
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# Install cocotb
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uv sync --group cocotb-test
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# Run tests (when simulator available)
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pytest tests/cocotb/testbenches/test_*_runner.py -v
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```
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## Test Results
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### ✅ Integration Tests: 9/9 Passing
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- test_apb4_simple_register
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- test_apb3_multiple_registers
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- test_axi4lite_nested_addrmap
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- test_register_array
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- test_get_verilog_sources
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- test_compile_rdl_and_export_with_custom_names
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- test_cpuif_generation[APB3Cpuif-apb3_intf]
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- test_cpuif_generation[APB4Cpuif-apb4_intf]
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- test_cpuif_generation[AXI4LiteCpuif-axi4lite_intf]
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### ✅ Existing Unit Tests: 56/56 Passing
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- No regressions introduced
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- 4 pre-existing failures in test_unroll.py remain unchanged
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### ✅ Security Checks
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- No vulnerabilities found in new dependencies (cocotb, cocotb-bus)
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- CodeQL analysis: 0 alerts
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## Design Decisions
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1. **Separate integration tests**: Created tests that run without a simulator for CI/CD friendliness
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2. **Relative imports**: Used proper Python package structure instead of sys.path manipulation
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3. **Multiple CPU interfaces**: Comprehensive coverage of all supported interfaces
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4. **BFM architecture**: Reusable Bus Functional Models for each protocol
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5. **Example script**: Provides easy-to-run demonstrations of code generation
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## Future Enhancements
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1. **CI Integration**: Add optional CI job with simulator for full cocotb tests
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2. **More test scenarios**: Coverage tests, error handling, corner cases
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3. **Avalon MM support**: Add testbenches for Avalon Memory-Mapped interface
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4. **Waveform verification**: Automated protocol compliance checking
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5. **Performance tests**: Bus utilization and throughput testing
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## Dependencies
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### Required
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- peakrdl-busdecoder (existing)
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- systemrdl-compiler (existing)
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### Optional (for simulation)
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- cocotb >= 1.8.0
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- cocotb-bus >= 0.2.1
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- iverilog or verilator (HDL simulator)
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## Notes
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- Integration tests run in CI without requiring a simulator
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- Full simulation tests are marked with pytest.skip when simulator not available
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- All code follows project conventions (ruff formatting, type hints)
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- Documentation includes both uv (project standard) and pip alternatives
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