diff --git a/pyproject.toml b/pyproject.toml
index fb41594..0c470ff 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -6,7 +6,10 @@ build-backend = "setuptools.build_meta"
 name = "peakrdl-busdecoder"
 version = "0.5.0"
 requires-python = ">=3.10"
-dependencies = ["jinja2>=3.1.6", "systemrdl-compiler~=1.30.1"]
+dependencies = [
+    "jinja2~=3.1",
+    "systemrdl-compiler~=1.30",
+]
 
 authors = [{ name = "Arnav Sacheti" }]
 description = "Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces"
diff --git a/uv.lock b/uv.lock
index e5ff9b8..82e42ab 100644
--- a/uv.lock
+++ b/uv.lock
@@ -641,9 +641,9 @@ tools = [
 
 [package.metadata]
 requires-dist = [
-    { name = "jinja2", specifier = ">=3.1.6" },
+    { name = "jinja2", specifier = "~=3.1" },
     { name = "peakrdl-cli", marker = "extra == 'cli'", specifier = ">=1.2.3" },
-    { name = "systemrdl-compiler", specifier = "~=1.30.1" },
+    { name = "systemrdl-compiler", specifier = "~=1.30" },
 ]
 provides-extras = ["cli"]