From 549ebe6085cbb71cd5b1f3c20a75951d68c4388d Mon Sep 17 00:00:00 2001
From: Arnav Sacheti <36746504+arnavsacheti@users.noreply.github.com>
Date: Wed, 24 Dec 2025 21:07:02 +0000
Subject: [PATCH] remove apb4 wr_sel assrt

---
 pyproject.toml                                 | 2 +-
 src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv | 2 --
 uv.lock                                        | 2 +-
 3 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/pyproject.toml b/pyproject.toml
index 71a8e92..1286e97 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -4,7 +4,7 @@ build-backend = "setuptools.build_meta"
 
 [project]
 name = "peakrdl-busdecoder"
-version = "0.6.2"
+version = "0.6.3"
 requires-python = ">=3.10"
 dependencies = [
     "jinja2~=3.1",
diff --git a/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv b/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
index 025a0a7..410e878 100644
--- a/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
+++ b/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
@@ -6,8 +6,6 @@
         assert_bad_data_width: assert($bits({{cpuif.signal("PWDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
             else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("PWDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
     end
-    assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("PSEL")}} && {{cpuif.signal("PWRITE")}} |-> ##1 ({{cpuif.signal("PREADY")}} || {{cpuif.signal("PSLVERR")}}))
-        else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
 `endif
 {%- endif %}
 
diff --git a/uv.lock b/uv.lock
index daaa454..1981945 100644
--- a/uv.lock
+++ b/uv.lock
@@ -608,7 +608,7 @@ wheels = [
 
 [[package]]
 name = "peakrdl-busdecoder"
-version = "0.6.2"
+version = "0.6.3"
 source = { editable = "." }
 dependencies = [
     { name = "jinja2" },