uvx format

2025-10-13 20:14:46 -07:00
parent 3eee8b9cdd
commit 54a199ca9c
17 changed files with 307 additions and 205 deletions
--- a/src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py
+++ b/src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py
@@ -1,4 +1,5 @@
 from systemrdl.node import AddressableNode
+
 from ..base_cpuif import BaseCpuif


@@ -17,9 +18,7 @@ class APB3Cpuif(BaseCpuif):
    @property
    def port_declaration(self) -> str:
        slave_ports: list[str] = ["apb3_intf.slave s_apb"]
-        master_ports: list[str] = list(
-            map(self._port_declaration, self.addressable_children)
-        )
+        master_ports: list[str] = list(map(self._port_declaration, self.addressable_children))

        return ",\n".join(slave_ports + master_ports)