uvx format
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@@ -6,18 +6,20 @@ from systemrdl.component import Field
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if TYPE_CHECKING:
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from systemrdl.node import Node
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class ReadSwacc(UDPDefinition):
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name = "rd_swacc"
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valid_components = {Field}
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valid_type = bool
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def get_unassigned_default(self, node: 'Node') -> Any:
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def get_unassigned_default(self, node: "Node") -> Any:
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return False
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class WriteSwacc(UDPDefinition):
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name = "wr_swacc"
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valid_components = {Field}
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valid_type = bool
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def get_unassigned_default(self, node: 'Node') -> Any:
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def get_unassigned_default(self, node: "Node") -> Any:
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return False
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