uvx format

This commit is contained in:
Arnav Sacheti
2025-10-13 20:14:46 -07:00
parent 3eee8b9cdd
commit 54a199ca9c
17 changed files with 307 additions and 205 deletions

View File

@@ -6,18 +6,20 @@ from systemrdl.component import Field
if TYPE_CHECKING:
from systemrdl.node import Node
class ReadSwacc(UDPDefinition):
name = "rd_swacc"
valid_components = {Field}
valid_type = bool
def get_unassigned_default(self, node: 'Node') -> Any:
def get_unassigned_default(self, node: "Node") -> Any:
return False
class WriteSwacc(UDPDefinition):
name = "wr_swacc"
valid_components = {Field}
valid_type = bool
def get_unassigned_default(self, node: 'Node') -> Any:
def get_unassigned_default(self, node: "Node") -> Any:
return False