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Update documentation to use correct repository name PeakRDL-BusDecoder and clarify project purpose (#7)

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* Initial plan

* Update documentation to use correct repository name PeakRDL-BusDecoder

Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>

* Update CONTRIBUTING.md and GitHub templates with correct repository name

Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>

* Update author to arnavsacheti and clarify bus decoder purpose in documentation

Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>

* Update author to 'Arnav Sacheti' and revise UDP documentation to reflect no current UDP support

Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>

---------

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
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Copilot
2025-10-23 23:23:10 -07:00
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docs/index.rst
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@@ -1,24 +1,32 @@
Introduction
============
PeakRDL-busdecoder is a free and open-source control & status register (CSR) compiler.
This code generator translates your SystemRDL register description into
a synthesizable SystemVerilog RTL module that can be easily instantiated into
your hardware design.
PeakRDL-BusDecoder is a free and open-source bus decoder generator for hierarchical register address maps.
This code generator translates your SystemRDL register description into a synthesizable
SystemVerilog RTL module that decodes CPU interface transactions and routes them to
multiple sub-address spaces (child addrmaps). This is particularly useful for:
* Generates fully synthesizable SystemVerilog RTL (IEEE 1800-2012)
* Options for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
* Configurable pipelining options for designs with fast clock rates.
* Creating hierarchical register maps with multiple sub-components
* Splitting a single CPU interface bus to serve multiple independent register blocks
* Organizing large register designs into logical sub-address spaces
* Implementing address decode logic for multi-drop bus architectures
The generated bus decoder provides:
* Fully synthesizable SystemVerilog RTL (IEEE 1800-2012)
* Support for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
* Address decode logic that routes transactions to child address maps
* Configurable pipelining options for designs with fast clock rates
* Broad support for SystemRDL 2.0 features
Quick Start
-----------
The easiest way to use PeakRDL-busdecoder is via the `PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_:
The easiest way to use PeakRDL-BusDecoder is via the `PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_:
.. code-block:: bash
# Install PeakRDL-busdecoder along with the command-line tool
# Install PeakRDL-BusDecoder along with the command-line tool
python3 -m pip install peakrdl-busdecoder[cli]
# Export!
@@ -29,15 +37,15 @@ Looking for VHDL?
-----------------
This project generates SystemVerilog RTL. If you prefer using VHDL, check out
the sister project which aims to be a feature-equivalent fork of
PeakRDL-busdecoder: `PeakRDL-busdecoder-VHDL <https://peakrdl-busdecoder-vhdl.readthedocs.io>`_
PeakRDL-BusDecoder: `PeakRDL-busdecoder-VHDL <https://peakrdl-busdecoder-vhdl.readthedocs.io>`_
Links
-----
- `Source repository <https://github.com/arnavsacheti/PeakRDL-busdecoder>`_
- `Release Notes <https://github.com/arnavsacheti/PeakRDL-busdecoder/releases>`_
- `Issue tracker <https://github.com/arnavsacheti/PeakRDL-busdecoder/issues>`_
- `Source repository <https://github.com/arnavsacheti/PeakRDL-BusDecoder>`_
- `Release Notes <https://github.com/arnavsacheti/PeakRDL-BusDecoder/releases>`_
- `Issue tracker <https://github.com/arnavsacheti/PeakRDL-BusDecoder/issues>`_
- `PyPi <https://pypi.org/project/peakrdl-busdecoder>`_
- `SystemRDL Specification <http://accellera.org/downloads/standards/systemrdl>`_
@@ -87,8 +95,3 @@ Links
:caption: Extended Properties
udps/intro
udps/read_buffering
udps/write_buffering
udps/extended_swacc
udps/signed
udps/fixedpoint