add colorized build/sim log propgate on error to all runners (#26)
* add colorized build/sim log propgate on error to all runners * add doctoring Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --------- Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
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@@ -11,6 +11,7 @@ from cocotb.triggers import Timer
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from tests.cocotb_lib.handle_utils import SignalHandle, resolve_handle
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class _Apb3SlaveShim:
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"""Accessor for the APB3 slave signals on the DUT."""
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@@ -128,16 +129,20 @@ async def test_apb3_address_decoding(dut) -> None:
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assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
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assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write direction"
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assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive write address"
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assert _get_int(entry["outputs"]["PWDATA"], index) == write_data, f"{master_name} must receive write data"
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assert _get_int(entry["outputs"]["PADDR"], index) == address, (
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f"{master_name} must receive write address"
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)
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assert _get_int(entry["outputs"]["PWDATA"], index) == write_data, (
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f"{master_name} must receive write data"
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)
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for other_name, other_idx in _all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert (
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_get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
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), f"{other_name}{other_idx} should remain idle during {txn['label']}"
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assert _get_int(other_entry["outputs"]["PSEL"], other_idx) == 0, (
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f"{other_name}{other_idx} should remain idle during {txn['label']}"
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)
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assert int(slave.PREADY.value) == 1, "Slave ready should mirror selected master"
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assert int(slave.PSLVERR.value) == 0, "Write should complete without error"
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@@ -164,16 +169,20 @@ async def test_apb3_address_decoding(dut) -> None:
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await Timer(1, units="ns")
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assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must assert PSEL for read"
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assert _get_int(entry["outputs"]["PWRITE"], index) == 0, f"{master_name} should clear write during read"
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assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive read address"
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assert _get_int(entry["outputs"]["PWRITE"], index) == 0, (
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f"{master_name} should clear write during read"
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)
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assert _get_int(entry["outputs"]["PADDR"], index) == address, (
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f"{master_name} must receive read address"
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)
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for other_name, other_idx in _all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert (
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_get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
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), f"{other_name}{other_idx} must stay idle during read of {txn['label']}"
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assert _get_int(other_entry["outputs"]["PSEL"], other_idx) == 0, (
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f"{other_name}{other_idx} must stay idle during read of {txn['label']}"
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)
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assert int(slave.PRDATA.value) == read_data, "Read data should propagate back to the slave"
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assert int(slave.PREADY.value) == 1, "Slave ready should acknowledge the read"
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