Refactor cpuif classes to use Interface abstraction (#14)
* Initial plan * Refactor cpuif classes to use Interface abstraction Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix type annotation consistency in Interface.signal() Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add runtime validation and documentation for indexer types Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Remove unused variable in SVInterface.signal() Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix master port directions in APB3 and APB4 flat interfaces Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix AXI4LiteCpuifFlat and apply code formatting Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * PSELx -> PSEL * cleanup marker warnings --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
This commit is contained in:
Copilot
@@ -1,48 +1,37 @@
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from typing import overload
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from typing import TYPE_CHECKING, overload
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from systemrdl.node import AddressableNode
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from ...utils import get_indexed_path
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from ..base_cpuif import BaseCpuif
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from .apb4_interface import APB4SVInterface
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if TYPE_CHECKING:
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from ...exporter import BusDecoderExporter
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class APB4Cpuif(BaseCpuif):
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template_path = "apb4_tmpl.sv"
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is_interface = True
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def _port_declaration(self, child: AddressableNode) -> str:
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base = f"apb4_intf.master m_apb_{child.inst_name}"
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def __init__(self, exp: "BusDecoderExporter") -> None:
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super().__init__(exp)
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self._interface = APB4SVInterface(self)
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# When unrolled, current_idx is set - append it to the name
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if child.current_idx is not None:
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base = f"{base}_{'_'.join(map(str, child.current_idx))}"
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# Only add array dimensions if this should be treated as an array
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if self.check_is_array(child):
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assert child.array_dimensions is not None
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return f"{base} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
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return base
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@property
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def is_interface(self) -> bool:
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return self._interface.is_interface
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@property
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def port_declaration(self) -> str:
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"""Returns the port declaration for the APB4 interface."""
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slave_ports: list[str] = ["apb4_intf.slave s_apb"]
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master_ports: list[str] = list(map(self._port_declaration, self.addressable_children))
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return ",\n".join(slave_ports + master_ports)
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return self._interface.get_port_declaration("s_apb", "m_apb_")
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@overload
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def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
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@overload
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def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
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def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
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if node is None or indexer is None:
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# Node is none, so this is a slave signal
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return f"s_apb.{signal}"
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# Master signal
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return f"m_apb_{get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)}.{signal}"
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return self._interface.signal(signal, node, indexer)
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def fanout(self, node: AddressableNode) -> str:
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fanout: dict[str, str] = {}
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@@ -1,50 +1,29 @@
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from typing import TYPE_CHECKING
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from systemrdl.node import AddressableNode
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from ...utils import get_indexed_path
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from ..base_cpuif import BaseCpuif
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from .apb4_interface import APB4FlatInterface
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if TYPE_CHECKING:
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from ...exporter import BusDecoderExporter
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class APB4CpuifFlat(BaseCpuif):
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template_path = "apb4_tmpl.sv"
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is_interface = False
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def _port_declaration(self, child: AddressableNode) -> list[str]:
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return [
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f"input logic {self.signal('PCLK', child)}",
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f"input logic {self.signal('PRESETn', child)}",
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f"output logic {self.signal('PSELx', child)}",
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f"output logic {self.signal('PENABLE', child)}",
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f"output logic {self.signal('PWRITE', child)}",
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f"output logic [{self.addr_width - 1}:0] {self.signal('PADDR', child)}",
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f"output logic [2:0] {self.signal('PPROT', child)}",
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f"output logic [{self.data_width - 1}:0] {self.signal('PWDATA', child)}",
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f"output logic [{self.data_width // 8 - 1}:0] {self.signal('PSTRB', child)}",
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f"input logic [{self.data_width - 1}:0] {self.signal('PRDATA', child)}",
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f"input logic {self.signal('PREADY', child)}",
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f"input logic {self.signal('PSLVERR', child)}",
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]
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def __init__(self, exp: "BusDecoderExporter") -> None:
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super().__init__(exp)
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self._interface = APB4FlatInterface(self)
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@property
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def is_interface(self) -> bool:
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return self._interface.is_interface
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@property
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def port_declaration(self) -> str:
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slave_ports: list[str] = [
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f"input logic {self.signal('PCLK')}",
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f"input logic {self.signal('PRESETn')}",
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f"input logic {self.signal('PSELx')}",
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f"input logic {self.signal('PENABLE')}",
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f"input logic {self.signal('PWRITE')}",
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f"input logic [{self.addr_width - 1}:0] {self.signal('PADDR')}",
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f"input logic [2:0] {self.signal('PPROT')}",
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f"input logic [{self.data_width - 1}:0] {self.signal('PWDATA')}",
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f"input logic [{self.data_width // 8 - 1}:0] {self.signal('PSTRB')}",
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f"output logic [{self.data_width - 1}:0] {self.signal('PRDATA')}",
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f"output logic {self.signal('PREADY')}",
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f"output logic {self.signal('PSLVERR')}",
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]
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master_ports: list[str] = []
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for child in self.addressable_children:
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master_ports.extend(self._port_declaration(child))
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return ",\n".join(slave_ports + master_ports)
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return self._interface.get_port_declaration("s_apb_", "m_apb_")
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def signal(
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self,
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@@ -52,27 +31,11 @@ class APB4CpuifFlat(BaseCpuif):
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node: AddressableNode | None = None,
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idx: str | int | None = None,
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) -> str:
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mapped_signal = "PSELx" if signal == "PSEL" else signal
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if node is None:
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# Node is none, so this is a slave signal
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return f"s_apb_{mapped_signal}"
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# Master signal
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base = f"m_apb_{node.inst_name}"
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if not self.check_is_array(node):
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# Not an array or an unrolled element
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if node.current_idx is not None:
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# This is a specific instance of an unrolled array
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return f"{base}_{mapped_signal}_{'_'.join(map(str, node.current_idx))}"
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return f"{base}_{mapped_signal}"
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# Is an array
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if idx is not None:
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return f"{base}_{mapped_signal}[{idx}]"
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return f"{base}_{mapped_signal}[N_{node.inst_name.upper()}S]"
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return self._interface.signal(signal, node, idx)
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def fanout(self, node: AddressableNode) -> str:
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fanout: dict[str, str] = {}
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fanout[self.signal("PSELx", node)] = (
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fanout[self.signal("PSEL", node)] = (
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f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
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)
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fanout[self.signal("PENABLE", node)] = self.signal("PENABLE")
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60
src/peakrdl_busdecoder/cpuif/apb4/apb4_interface.py
Normal file
60
src/peakrdl_busdecoder/cpuif/apb4/apb4_interface.py
Normal file
@@ -0,0 +1,60 @@
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"""APB4-specific interface implementations."""
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from systemrdl.node import AddressableNode
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from ..interface import FlatInterface, SVInterface
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class APB4SVInterface(SVInterface):
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"""APB4 SystemVerilog interface."""
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def get_interface_type(self) -> str:
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return "apb4_intf"
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def get_slave_name(self) -> str:
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return "s_apb"
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def get_master_prefix(self) -> str:
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return "m_apb_"
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class APB4FlatInterface(FlatInterface):
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"""APB4 flat signal interface."""
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def get_slave_prefix(self) -> str:
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return "s_apb_"
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def get_master_prefix(self) -> str:
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return "m_apb_"
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def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
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return [
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f"input logic {slave_prefix}PCLK",
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f"input logic {slave_prefix}PRESETn",
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f"input logic {slave_prefix}PSEL",
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f"input logic {slave_prefix}PENABLE",
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f"input logic {slave_prefix}PWRITE",
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f"input logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}PADDR",
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f"input logic [2:0] {slave_prefix}PPROT",
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f"input logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PWDATA",
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f"input logic [{self.cpuif.data_width // 8 - 1}:0] {slave_prefix}PSTRB",
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f"output logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PRDATA",
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f"output logic {slave_prefix}PREADY",
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f"output logic {slave_prefix}PSLVERR",
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]
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def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
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return [
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f"output logic {self.signal('PCLK', child)}",
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f"output logic {self.signal('PRESETn', child)}",
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f"output logic {self.signal('PSEL', child)}",
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f"output logic {self.signal('PENABLE', child)}",
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f"output logic {self.signal('PWRITE', child)}",
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f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('PADDR', child)}",
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f"output logic [2:0] {self.signal('PPROT', child)}",
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f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('PWDATA', child)}",
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f"output logic [{self.cpuif.data_width // 8 - 1}:0] {self.signal('PSTRB', child)}",
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f"input logic [{self.cpuif.data_width - 1}:0] {self.signal('PRDATA', child)}",
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f"input logic {self.signal('PREADY', child)}",
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f"input logic {self.signal('PSLVERR', child)}",
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]
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