Refactor cpuif classes to use Interface abstraction (#14)
* Initial plan * Refactor cpuif classes to use Interface abstraction Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix type annotation consistency in Interface.signal() Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add runtime validation and documentation for indexer types Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Remove unused variable in SVInterface.signal() Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix master port directions in APB3 and APB4 flat interfaces Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix AXI4LiteCpuifFlat and apply code formatting Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * PSELx -> PSEL * cleanup marker warnings --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
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Copilot
190
src/peakrdl_busdecoder/cpuif/interface.py
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190
src/peakrdl_busdecoder/cpuif/interface.py
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"""Interface abstraction for handling flat and non-flat signal declarations."""
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from abc import ABC, abstractmethod
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from typing import TYPE_CHECKING
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from systemrdl.node import AddressableNode
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if TYPE_CHECKING:
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from .base_cpuif import BaseCpuif
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class Interface(ABC):
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"""Abstract base class for interface signal handling."""
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def __init__(self, cpuif: "BaseCpuif") -> None:
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self.cpuif = cpuif
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@property
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@abstractmethod
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def is_interface(self) -> bool:
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"""Whether this uses SystemVerilog interfaces."""
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...
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@abstractmethod
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def get_port_declaration(self, slave_name: str, master_prefix: str) -> str:
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"""
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Generate port declarations for the interface.
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Args:
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slave_name: Name of the slave interface/signal prefix
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master_prefix: Prefix for master interfaces/signals
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Returns:
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Port declarations as a string
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"""
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...
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@abstractmethod
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def signal(
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self,
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signal: str,
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node: AddressableNode | None = None,
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indexer: str | int | None = None,
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) -> str:
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"""
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Generate signal reference.
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Args:
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signal: Signal name
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node: Optional addressable node for master signals
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indexer: Optional indexer for arrays.
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For SVInterface: str like "i" or "gi" for loop indices
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For FlatInterface: str or int for array subscript
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Returns:
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Signal reference as a string
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"""
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...
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class SVInterface(Interface):
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"""SystemVerilog interface-based signal handling."""
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@property
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def is_interface(self) -> bool:
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return True
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def get_port_declaration(self, slave_name: str, master_prefix: str) -> str:
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"""Generate SystemVerilog interface port declarations."""
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slave_ports: list[str] = [f"{self.get_interface_type()}.slave {slave_name}"]
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master_ports: list[str] = []
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for child in self.cpuif.addressable_children:
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base = f"{self.get_interface_type()}.master {master_prefix}{child.inst_name}"
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# When unrolled, current_idx is set - append it to the name
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if child.current_idx is not None:
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base = f"{base}_{'_'.join(map(str, child.current_idx))}"
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# Only add array dimensions if this should be treated as an array
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if self.cpuif.check_is_array(child):
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assert child.array_dimensions is not None
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base = f"{base} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
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master_ports.append(base)
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return ",\n".join(slave_ports + master_ports)
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def signal(
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self,
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signal: str,
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node: AddressableNode | None = None,
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indexer: str | int | None = None,
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) -> str:
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"""Generate SystemVerilog interface signal reference."""
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from ..utils import get_indexed_path
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# SVInterface only supports string indexers (loop variable names like "i", "gi")
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if indexer is not None and not isinstance(indexer, str):
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raise TypeError(f"SVInterface.signal() requires string indexer, got {type(indexer).__name__}")
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if node is None or indexer is None:
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# Node is none, so this is a slave signal
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slave_name = self.get_slave_name()
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return f"{slave_name}.{signal}"
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# Master signal
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master_prefix = self.get_master_prefix()
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return f"{master_prefix}{get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)}.{signal}"
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@abstractmethod
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def get_interface_type(self) -> str:
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"""Get the SystemVerilog interface type name."""
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...
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@abstractmethod
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def get_slave_name(self) -> str:
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"""Get the slave interface instance name."""
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...
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@abstractmethod
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def get_master_prefix(self) -> str:
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"""Get the master interface name prefix."""
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...
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class FlatInterface(Interface):
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"""Flat signal-based interface handling."""
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@property
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def is_interface(self) -> bool:
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return False
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def get_port_declaration(self, slave_name: str, master_prefix: str) -> str:
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"""Generate flat port declarations."""
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slave_ports = self._get_slave_port_declarations(slave_name)
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master_ports: list[str] = []
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for child in self.cpuif.addressable_children:
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master_ports.extend(self._get_master_port_declarations(child, master_prefix))
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return ",\n".join(slave_ports + master_ports)
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def signal(
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self,
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signal: str,
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node: AddressableNode | None = None,
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indexer: str | int | None = None,
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) -> str:
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"""Generate flat signal reference."""
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if node is None:
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# Node is none, so this is a slave signal
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slave_prefix = self.get_slave_prefix()
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return f"{slave_prefix}{signal}"
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# Master signal
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master_prefix = self.get_master_prefix()
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base = f"{master_prefix}{node.inst_name}"
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if not self.cpuif.check_is_array(node):
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# Not an array or an unrolled element
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if node.current_idx is not None:
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# This is a specific instance of an unrolled array
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return f"{base}_{signal}_{'_'.join(map(str, node.current_idx))}"
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return f"{base}_{signal}"
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# Is an array
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if indexer is not None:
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return f"{base}_{signal}[{indexer}]"
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return f"{base}_{signal}[N_{node.inst_name.upper()}S]"
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@abstractmethod
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def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
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"""Get slave port declarations."""
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...
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@abstractmethod
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def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
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"""Get master port declarations for a child node."""
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...
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@abstractmethod
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def get_slave_prefix(self) -> str:
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"""Get the slave signal name prefix."""
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...
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@abstractmethod
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def get_master_prefix(self) -> str:
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"""Get the master signal name prefix."""
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...
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