Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

tests/test_onread_onwrite/regblock.rdl

@@ -0,0 +1,61 @@
+addrmap top {
+
+    reg {
+        field {
+            sw=rw; hw=na;
+            onread = rclr;
+        } f1[7:0] = 0xF0;
+
+        field {
+            sw=rw; hw=na;
+            onread = rset;
+        } f2[15:8] = 0x0F;
+    } r1;
+
+
+    reg {
+        field {
+            sw=rw; hw=na;
+            onwrite = woset;
+        } f1[3:0] = 0x0;
+
+        field {
+            sw=rw; hw=na;
+            onwrite = woclr;
+        } f2[7:4] = 0xF;
+
+        field {
+            sw=rw; hw=na;
+            onwrite = wot;
+        } f3[11:8] = 0x0;
+    } r2;
+
+    reg {
+        field {
+            sw=rw; hw=na;
+            onwrite = wzs;
+        } f1[3:0] = 0x0;
+
+        field {
+            sw=rw; hw=na;
+            onwrite = wzc;
+        } f2[7:4] = 0xF;
+
+        field {
+            sw=rw; hw=na;
+            onwrite = wzt;
+        } f3[11:8] = 0x0;
+    } r3;
+
+    reg {
+        field {
+            sw=rw; hw=na;
+            onwrite = wclr;
+        } f1[7:0] = 0xF0;
+
+        field {
+            sw=rw; hw=na;
+            onwrite = wset;
+        } f2[15:8] = 0x0F;
+    } r4;
+};

tests/test_onread_onwrite/tb_template.sv

@@ -0,0 +1,30 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    cpuif.assert_read('h0, 'h0F_F0);
+    cpuif.assert_read('h0, 'hFF_00);
+    cpuif.write      ('h0, 'h00_FF);
+    cpuif.assert_read('h0, 'h00_FF);
+    cpuif.assert_read('h0, 'hFF_00);
+
+    cpuif.assert_read('h4, 'h0_F_0);
+    cpuif.write      ('h4, 'h1_1_1);
+    cpuif.assert_read('h4, 'h1_E_1);
+    cpuif.write      ('h4, 'h1_2_2);
+    cpuif.assert_read('h4, 'h0_C_3);
+
+    cpuif.assert_read('h8, 'h0_F_0);
+    cpuif.write      ('h8, 'hE_E_E);
+    cpuif.assert_read('h8, 'h1_E_1);
+    cpuif.write      ('h8, 'hE_D_D);
+    cpuif.assert_read('h8, 'h0_C_3);
+
+    cpuif.assert_read('hC, 'h0F_F0);
+    cpuif.write      ('hC, 'h12_34);
+    cpuif.assert_read('hC, 'hFF_00);
+{% endblock %}

tests/test_onread_onwrite/testcase.py

@@ -0,0 +1,5 @@
+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()