Tests/cocotb (#19)
* wip * reorg * update sv int * apb4 working * apb3 working * version bump + ignore runner warning * remove redundant check * adding log on failure * cleaning up verilator version issue * devcontainer * Fix missing libpython in GitHub Actions CI environment (#21) * Initial plan * Install libpython in GitHub Actions for cocotb tests Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: Copilot <198982749+Copilot@users.noreply.github.com>
This commit is contained in:
Arnav Sacheti
@@ -1,15 +1,19 @@
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"""APB3 smoke tests for generated multi-register design."""
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"""APB3 smoke tests generated from SystemRDL sources."""
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from __future__ import annotations
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import json
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import os
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from typing import Any, Iterable
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import cocotb
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from cocotb.triggers import Timer
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WRITE_ADDR = 0x0
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READ_ADDR = 0x8
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WRITE_DATA = 0xCAFEBABE
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READ_DATA = 0x0BAD_F00D
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from tests.cocotb_lib.handle_utils import SignalHandle, resolve_handle
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class _Apb3SlaveShim:
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"""Accessor for the APB3 slave signals on the DUT."""
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def __init__(self, dut):
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prefix = "s_apb"
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self.PSEL = getattr(dut, f"{prefix}_PSEL")
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@@ -22,102 +26,161 @@ class _Apb3SlaveShim:
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self.PSLVERR = getattr(dut, f"{prefix}_PSLVERR")
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class _Apb3MasterShim:
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def __init__(self, dut, base: str):
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self.PSEL = getattr(dut, f"{base}_PSEL")
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self.PENABLE = getattr(dut, f"{base}_PENABLE")
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self.PWRITE = getattr(dut, f"{base}_PWRITE")
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self.PADDR = getattr(dut, f"{base}_PADDR")
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self.PWDATA = getattr(dut, f"{base}_PWDATA")
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self.PRDATA = getattr(dut, f"{base}_PRDATA")
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self.PREADY = getattr(dut, f"{base}_PREADY")
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self.PSLVERR = getattr(dut, f"{base}_PSLVERR")
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def _load_config() -> dict[str, Any]:
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payload = os.environ.get("RDL_TEST_CONFIG")
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if payload is None:
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raise RuntimeError("RDL_TEST_CONFIG environment variable was not provided")
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return json.loads(payload)
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def _apb3_slave(dut):
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return getattr(dut, "s_apb", None) or _Apb3SlaveShim(dut)
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def _resolve(handle, indices: Iterable[int]):
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return resolve_handle(handle, indices)
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def _apb3_master(dut, base: str):
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return getattr(dut, base, None) or _Apb3MasterShim(dut, base)
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def _set_value(handle, indices: Iterable[int], value: int) -> None:
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_resolve(handle, indices).value = value
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def _get_int(handle, indices: Iterable[int]) -> int:
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return int(_resolve(handle, indices).value)
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def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dict[str, Any]]:
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table: dict[str, dict[str, Any]] = {}
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for master in masters_cfg:
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prefix = master["port_prefix"]
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entry = {
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"indices": [tuple(idx) for idx in master["indices"]] or [tuple()],
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"outputs": {
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"PSEL": SignalHandle(dut, f"{prefix}_PSEL"),
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"PENABLE": SignalHandle(dut, f"{prefix}_PENABLE"),
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"PWRITE": SignalHandle(dut, f"{prefix}_PWRITE"),
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"PADDR": SignalHandle(dut, f"{prefix}_PADDR"),
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"PWDATA": SignalHandle(dut, f"{prefix}_PWDATA"),
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},
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"inputs": {
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"PRDATA": SignalHandle(dut, f"{prefix}_PRDATA"),
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"PREADY": SignalHandle(dut, f"{prefix}_PREADY"),
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"PSLVERR": SignalHandle(dut, f"{prefix}_PSLVERR"),
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},
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}
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table[master["inst_name"]] = entry
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return table
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def _all_index_pairs(table: dict[str, dict[str, Any]]):
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for name, entry in table.items():
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for idx in entry["indices"]:
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yield name, idx
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def _write_pattern(address: int, width: int) -> int:
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mask = (1 << width) - 1
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return ((address * 0x2041) ^ 0xCAFEBABE) & mask
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def _read_pattern(address: int, width: int) -> int:
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mask = (1 << width) - 1
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return ((address ^ 0x0BAD_F00D) + width) & mask
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@cocotb.test()
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async def test_apb3_read_write_paths(dut):
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"""Exercise APB3 slave interface and observe master fanout."""
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s_apb = _apb3_slave(dut)
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masters = {
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"reg1": _apb3_master(dut, "m_apb_reg1"),
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"reg2": _apb3_master(dut, "m_apb_reg2"),
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"reg3": _apb3_master(dut, "m_apb_reg3"),
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}
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async def test_apb3_address_decoding(dut) -> None:
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"""Exercise the APB3 slave interface against sampled register addresses."""
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config = _load_config()
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slave = _Apb3SlaveShim(dut)
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masters = _build_master_table(dut, config["masters"])
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s_apb.PSEL.value = 0
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s_apb.PENABLE.value = 0
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s_apb.PWRITE.value = 0
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s_apb.PADDR.value = 0
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s_apb.PWDATA.value = 0
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slave.PSEL.value = 0
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slave.PENABLE.value = 0
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slave.PWRITE.value = 0
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slave.PADDR.value = 0
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slave.PWDATA.value = 0
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for master in masters.values():
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master.PRDATA.value = 0
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master.PREADY.value = 0
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master.PSLVERR.value = 0
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for master_name, idx in _all_index_pairs(masters):
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entry = masters[master_name]
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_set_value(entry["inputs"]["PRDATA"], idx, 0)
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_set_value(entry["inputs"]["PREADY"], idx, 0)
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_set_value(entry["inputs"]["PSLVERR"], idx, 0)
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await Timer(1, units="ns")
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# Write to reg1
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masters["reg1"].PREADY.value = 1
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s_apb.PADDR.value = WRITE_ADDR
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s_apb.PWDATA.value = WRITE_DATA
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s_apb.PWRITE.value = 1
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s_apb.PSEL.value = 1
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s_apb.PENABLE.value = 1
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addr_mask = (1 << config["address_width"]) - 1
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await Timer(1, units="ns")
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for txn in config["transactions"]:
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master_name = txn["master"]
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index = tuple(txn["index"])
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entry = masters[master_name]
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assert int(masters["reg1"].PSEL.value) == 1, "reg1 should be selected for write"
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assert int(masters["reg1"].PWRITE.value) == 1, "Write should propagate to master"
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assert int(masters["reg1"].PADDR.value) == WRITE_ADDR, "Address should reach selected master"
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assert int(masters["reg1"].PWDATA.value) == WRITE_DATA, "Write data should fan out"
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address = txn["address"] & addr_mask
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write_data = _write_pattern(address, config["data_width"])
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for name, master in masters.items():
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if name != "reg1":
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assert int(master.PSEL.value) == 0, f"{name} must idle during reg1 write"
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_set_value(entry["inputs"]["PREADY"], index, 1)
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_set_value(entry["inputs"]["PSLVERR"], index, 0)
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assert int(s_apb.PREADY.value) == 1, "Ready must reflect selected master"
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assert int(s_apb.PSLVERR.value) == 0, "Write should not signal error"
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slave.PADDR.value = address
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slave.PWDATA.value = write_data
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slave.PWRITE.value = 1
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slave.PSEL.value = 1
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slave.PENABLE.value = 1
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s_apb.PSEL.value = 0
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s_apb.PENABLE.value = 0
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s_apb.PWRITE.value = 0
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masters["reg1"].PREADY.value = 0
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await Timer(1, units="ns")
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await Timer(1, units="ns")
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# Read from reg3
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masters["reg3"].PRDATA.value = READ_DATA
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masters["reg3"].PREADY.value = 1
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masters["reg3"].PSLVERR.value = 0
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assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
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assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write direction"
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assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive write address"
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assert _get_int(entry["outputs"]["PWDATA"], index) == write_data, f"{master_name} must receive write data"
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s_apb.PADDR.value = READ_ADDR
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s_apb.PSEL.value = 1
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s_apb.PENABLE.value = 1
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s_apb.PWRITE.value = 0
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for other_name, other_idx in _all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert (
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_get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
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), f"{other_name}{other_idx} should remain idle during {txn['label']}"
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await Timer(1, units="ns")
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assert int(slave.PREADY.value) == 1, "Slave ready should mirror selected master"
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assert int(slave.PSLVERR.value) == 0, "Write should complete without error"
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assert int(masters["reg3"].PSEL.value) == 1, "reg3 should be selected for read"
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assert int(masters["reg3"].PWRITE.value) == 0, "Read should clear write"
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assert int(masters["reg3"].PADDR.value) == READ_ADDR, "Address should reach read target"
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slave.PSEL.value = 0
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slave.PENABLE.value = 0
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slave.PWRITE.value = 0
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_set_value(entry["inputs"]["PREADY"], index, 0)
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await Timer(1, units="ns")
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for name, master in masters.items():
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if name != "reg3":
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assert int(master.PSEL.value) == 0, f"{name} must idle during reg3 read"
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# ------------------------------------------------------------------
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# Read phase
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# ------------------------------------------------------------------
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read_data = _read_pattern(address, config["data_width"])
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_set_value(entry["inputs"]["PRDATA"], index, read_data)
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_set_value(entry["inputs"]["PREADY"], index, 1)
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_set_value(entry["inputs"]["PSLVERR"], index, 0)
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assert int(s_apb.PRDATA.value) == READ_DATA, "Read data should return to slave"
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assert int(s_apb.PREADY.value) == 1, "Read should acknowledge"
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assert int(s_apb.PSLVERR.value) == 0, "Read should not signal error"
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slave.PADDR.value = address
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slave.PWRITE.value = 0
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slave.PSEL.value = 1
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slave.PENABLE.value = 1
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s_apb.PSEL.value = 0
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s_apb.PENABLE.value = 0
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masters["reg3"].PREADY.value = 0
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await Timer(1, units="ns")
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await Timer(1, units="ns")
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assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must assert PSEL for read"
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assert _get_int(entry["outputs"]["PWRITE"], index) == 0, f"{master_name} should clear write during read"
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assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive read address"
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for other_name, other_idx in _all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert (
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_get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
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), f"{other_name}{other_idx} must stay idle during read of {txn['label']}"
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assert int(slave.PRDATA.value) == read_data, "Read data should propagate back to the slave"
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assert int(slave.PREADY.value) == 1, "Slave ready should acknowledge the read"
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assert int(slave.PSLVERR.value) == 0, "Read should not signal an error"
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slave.PSEL.value = 0
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slave.PENABLE.value = 0
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_set_value(entry["inputs"]["PREADY"], index, 0)
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_set_value(entry["inputs"]["PRDATA"], index, 0)
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await Timer(1, units="ns")
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@@ -1,5 +1,8 @@
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"""Pytest wrapper launching the APB3 cocotb smoke test."""
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"""Pytest wrapper launching the APB3 cocotb smoke tests."""
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from __future__ import annotations
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import json
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from pathlib import Path
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import pytest
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@@ -11,20 +14,25 @@ try: # pragma: no cover - optional dependency shim
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except ImportError: # pragma: no cover
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from cocotb_tools.runner import get_runner
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from tests.cocotb_lib.utils import compile_rdl_and_export, get_verilog_sources
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from tests.cocotb_lib import RDL_CASES
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from tests.cocotb_lib.utils import get_verilog_sources, prepare_cpuif_case
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@pytest.mark.simulation
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@pytest.mark.verilator
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def test_apb3_smoke(tmp_path: Path) -> None:
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"""Compile the APB3 design and execute the cocotb smoke test."""
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@pytest.mark.parametrize(("rdl_file", "top_name"), RDL_CASES, ids=[case[1] for case in RDL_CASES])
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def test_apb3_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
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"""Compile each APB3 design variant and execute the cocotb smoke test."""
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repo_root = Path(__file__).resolve().parents[4]
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rdl_path = repo_root / "tests" / "cocotb_lib" / "rdl" / rdl_file
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build_root = tmp_path / top_name
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module_path, package_path = compile_rdl_and_export(
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str(repo_root / "tests" / "cocotb_lib" / "multiple_reg.rdl"),
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"multi_reg",
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tmp_path,
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module_path, package_path, config = prepare_cpuif_case(
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str(rdl_path),
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top_name,
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build_root,
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cpuif_cls=APB3CpuifFlat,
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control_signal="PSEL",
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)
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sources = get_verilog_sources(
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@@ -34,17 +42,18 @@ def test_apb3_smoke(tmp_path: Path) -> None:
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)
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runner = get_runner("verilator")
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build_dir = tmp_path / "sim_build"
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sim_build = build_root / "sim_build"
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runner.build(
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sources=sources,
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hdl_toplevel=module_path.stem,
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build_dir=build_dir,
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build_dir=sim_build,
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)
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runner.test(
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hdl_toplevel=module_path.stem,
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test_module="tests.cocotb.apb3.smoke.test_register_access",
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build_dir=build_dir,
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log_file=str(tmp_path / "sim.log"),
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build_dir=sim_build,
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log_file=str(build_root / "simulation.log"),
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extra_env={"RDL_TEST_CONFIG": json.dumps(config)},
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)
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@@ -1,15 +1,19 @@
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"""APB4 smoke tests using generated multi-register design."""
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"""APB4 smoke tests generated from SystemRDL sources."""
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from __future__ import annotations
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import json
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import os
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from typing import Any, Iterable
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import cocotb
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from cocotb.triggers import Timer
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WRITE_ADDR = 0x4
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READ_ADDR = 0x8
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WRITE_DATA = 0x1234_5678
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READ_DATA = 0x89AB_CDEF
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from tests.cocotb_lib.handle_utils import SignalHandle, resolve_handle
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class _Apb4SlaveShim:
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"""Lightweight accessor for the APB4 slave side of the DUT."""
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def __init__(self, dut):
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prefix = "s_apb"
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self.PSEL = getattr(dut, f"{prefix}_PSEL")
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@@ -24,115 +28,175 @@ class _Apb4SlaveShim:
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self.PSLVERR = getattr(dut, f"{prefix}_PSLVERR")
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class _Apb4MasterShim:
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def __init__(self, dut, base: str):
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self.PSEL = getattr(dut, f"{base}_PSEL")
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self.PENABLE = getattr(dut, f"{base}_PENABLE")
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self.PWRITE = getattr(dut, f"{base}_PWRITE")
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self.PADDR = getattr(dut, f"{base}_PADDR")
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self.PPROT = getattr(dut, f"{base}_PPROT")
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self.PWDATA = getattr(dut, f"{base}_PWDATA")
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self.PSTRB = getattr(dut, f"{base}_PSTRB")
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self.PRDATA = getattr(dut, f"{base}_PRDATA")
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self.PREADY = getattr(dut, f"{base}_PREADY")
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self.PSLVERR = getattr(dut, f"{base}_PSLVERR")
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def _load_config() -> dict[str, Any]:
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"""Read the JSON payload describing the generated register topology."""
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payload = os.environ.get("RDL_TEST_CONFIG")
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if payload is None:
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raise RuntimeError("RDL_TEST_CONFIG environment variable was not provided")
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return json.loads(payload)
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def _apb4_slave(dut):
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return getattr(dut, "s_apb", None) or _Apb4SlaveShim(dut)
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def _resolve(handle, indices: Iterable[int]):
|
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"""Index into hierarchical cocotb handles."""
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return resolve_handle(handle, indices)
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def _apb4_master(dut, base: str):
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return getattr(dut, base, None) or _Apb4MasterShim(dut, base)
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def _set_value(handle, indices: Iterable[int], value: int) -> None:
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_resolve(handle, indices).value = value
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|
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|
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def _get_int(handle, indices: Iterable[int]) -> int:
|
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return int(_resolve(handle, indices).value)
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|
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|
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def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dict[str, Any]]:
|
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table: dict[str, dict[str, Any]] = {}
|
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for master in masters_cfg:
|
||||
port_prefix = master["port_prefix"]
|
||||
entry = {
|
||||
"port_prefix": port_prefix,
|
||||
"indices": [tuple(idx) for idx in master["indices"]] or [tuple()],
|
||||
"outputs": {
|
||||
"PSEL": SignalHandle(dut, f"{port_prefix}_PSEL"),
|
||||
"PENABLE": SignalHandle(dut, f"{port_prefix}_PENABLE"),
|
||||
"PWRITE": SignalHandle(dut, f"{port_prefix}_PWRITE"),
|
||||
"PADDR": SignalHandle(dut, f"{port_prefix}_PADDR"),
|
||||
"PPROT": SignalHandle(dut, f"{port_prefix}_PPROT"),
|
||||
"PWDATA": SignalHandle(dut, f"{port_prefix}_PWDATA"),
|
||||
"PSTRB": SignalHandle(dut, f"{port_prefix}_PSTRB"),
|
||||
},
|
||||
"inputs": {
|
||||
"PRDATA": SignalHandle(dut, f"{port_prefix}_PRDATA"),
|
||||
"PREADY": SignalHandle(dut, f"{port_prefix}_PREADY"),
|
||||
"PSLVERR": SignalHandle(dut, f"{port_prefix}_PSLVERR"),
|
||||
},
|
||||
}
|
||||
table[master["inst_name"]] = entry
|
||||
return table
|
||||
|
||||
|
||||
def _all_index_pairs(table: dict[str, dict[str, Any]]):
|
||||
for name, entry in table.items():
|
||||
for idx in entry["indices"]:
|
||||
yield name, idx
|
||||
|
||||
|
||||
def _write_pattern(address: int, width: int) -> int:
|
||||
mask = (1 << width) - 1
|
||||
return ((address * 0x1021) ^ 0x1357_9BDF) & mask
|
||||
|
||||
|
||||
def _read_pattern(address: int, width: int) -> int:
|
||||
mask = (1 << width) - 1
|
||||
return ((address ^ 0xDEAD_BEE5) + width) & mask
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def test_apb4_read_write_paths(dut):
|
||||
"""Drive APB4 slave signals and observe master activity."""
|
||||
s_apb = _apb4_slave(dut)
|
||||
masters = {
|
||||
"reg1": _apb4_master(dut, "m_apb_reg1"),
|
||||
"reg2": _apb4_master(dut, "m_apb_reg2"),
|
||||
"reg3": _apb4_master(dut, "m_apb_reg3"),
|
||||
}
|
||||
async def test_apb4_address_decoding(dut) -> None:
|
||||
"""Drive the APB4 slave interface and verify master fanout across all sampled registers."""
|
||||
config = _load_config()
|
||||
slave = _Apb4SlaveShim(dut)
|
||||
masters = _build_master_table(dut, config["masters"])
|
||||
|
||||
# Default slave side inputs
|
||||
s_apb.PSEL.value = 0
|
||||
s_apb.PENABLE.value = 0
|
||||
s_apb.PWRITE.value = 0
|
||||
s_apb.PADDR.value = 0
|
||||
s_apb.PWDATA.value = 0
|
||||
s_apb.PPROT.value = 0
|
||||
s_apb.PSTRB.value = 0
|
||||
slave.PSEL.value = 0
|
||||
slave.PENABLE.value = 0
|
||||
slave.PWRITE.value = 0
|
||||
slave.PADDR.value = 0
|
||||
slave.PPROT.value = 0
|
||||
slave.PWDATA.value = 0
|
||||
slave.PSTRB.value = 0
|
||||
|
||||
for master in masters.values():
|
||||
master.PRDATA.value = 0
|
||||
master.PREADY.value = 0
|
||||
master.PSLVERR.value = 0
|
||||
for master_name, idx in _all_index_pairs(masters):
|
||||
entry = masters[master_name]
|
||||
_set_value(entry["inputs"]["PRDATA"], idx, 0)
|
||||
_set_value(entry["inputs"]["PREADY"], idx, 0)
|
||||
_set_value(entry["inputs"]["PSLVERR"], idx, 0)
|
||||
|
||||
await Timer(1, units="ns")
|
||||
|
||||
# ------------------------------------------------------------------
|
||||
# Write transfer to reg2
|
||||
# ------------------------------------------------------------------
|
||||
masters["reg2"].PREADY.value = 1
|
||||
s_apb.PADDR.value = WRITE_ADDR
|
||||
s_apb.PWDATA.value = WRITE_DATA
|
||||
s_apb.PSTRB.value = 0xF
|
||||
s_apb.PPROT.value = 0
|
||||
s_apb.PWRITE.value = 1
|
||||
s_apb.PSEL.value = 1
|
||||
s_apb.PENABLE.value = 1
|
||||
addr_mask = (1 << config["address_width"]) - 1
|
||||
strobe_mask = (1 << config["byte_width"]) - 1
|
||||
|
||||
await Timer(1, units="ns")
|
||||
for txn in config["transactions"]:
|
||||
master_name = txn["master"]
|
||||
index = tuple(txn["index"])
|
||||
entry = masters[master_name]
|
||||
|
||||
assert int(masters["reg2"].PSEL.value) == 1, "reg2 must be selected for write"
|
||||
assert int(masters["reg2"].PWRITE.value) == 1, "Write strobes should propagate"
|
||||
assert int(masters["reg2"].PADDR.value) == WRITE_ADDR, "Address should fan out"
|
||||
assert int(masters["reg2"].PWDATA.value) == WRITE_DATA, "Write data should fan out"
|
||||
address = txn["address"] & addr_mask
|
||||
write_data = _write_pattern(address, config["data_width"])
|
||||
|
||||
for name, master in masters.items():
|
||||
if name != "reg2":
|
||||
assert int(master.PSEL.value) == 0, f"{name} should remain idle on write"
|
||||
# Prime master-side inputs for the write phase
|
||||
_set_value(entry["inputs"]["PREADY"], index, 1)
|
||||
_set_value(entry["inputs"]["PSLVERR"], index, 0)
|
||||
|
||||
assert int(s_apb.PREADY.value) == 1, "Ready should mirror selected master"
|
||||
assert int(s_apb.PSLVERR.value) == 0, "No error expected on successful write"
|
||||
slave.PADDR.value = address
|
||||
slave.PWDATA.value = write_data
|
||||
slave.PSTRB.value = strobe_mask
|
||||
slave.PPROT.value = 0
|
||||
slave.PWRITE.value = 1
|
||||
slave.PSEL.value = 1
|
||||
slave.PENABLE.value = 1
|
||||
|
||||
# Return to idle
|
||||
s_apb.PSEL.value = 0
|
||||
s_apb.PENABLE.value = 0
|
||||
s_apb.PWRITE.value = 0
|
||||
masters["reg2"].PREADY.value = 0
|
||||
await Timer(1, units="ns")
|
||||
await Timer(1, units="ns")
|
||||
|
||||
# ------------------------------------------------------------------
|
||||
# Read transfer from reg3
|
||||
# ------------------------------------------------------------------
|
||||
masters["reg3"].PRDATA.value = READ_DATA
|
||||
masters["reg3"].PREADY.value = 1
|
||||
masters["reg3"].PSLVERR.value = 0
|
||||
assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
|
||||
assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write intent"
|
||||
assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive write address"
|
||||
assert _get_int(entry["outputs"]["PWDATA"], index) == write_data, f"{master_name} must receive write data"
|
||||
assert _get_int(entry["outputs"]["PSTRB"], index) == strobe_mask, f"{master_name} must receive full strobes"
|
||||
|
||||
s_apb.PADDR.value = READ_ADDR
|
||||
s_apb.PSEL.value = 1
|
||||
s_apb.PENABLE.value = 1
|
||||
s_apb.PWRITE.value = 0
|
||||
for other_name, other_idx in _all_index_pairs(masters):
|
||||
if other_name == master_name and other_idx == index:
|
||||
continue
|
||||
other_entry = masters[other_name]
|
||||
assert (
|
||||
_get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
|
||||
), f"{other_name}{other_idx} should remain idle during {txn['label']}"
|
||||
|
||||
await Timer(1, units="ns")
|
||||
assert int(slave.PREADY.value) == 1, "Slave ready should reflect selected master"
|
||||
assert int(slave.PSLVERR.value) == 0, "No error expected during write"
|
||||
|
||||
assert int(masters["reg3"].PSEL.value) == 1, "reg3 must be selected for read"
|
||||
assert int(masters["reg3"].PWRITE.value) == 0, "Read should deassert write"
|
||||
assert int(masters["reg3"].PADDR.value) == READ_ADDR, "Read address should propagate"
|
||||
# Return to idle for next transaction
|
||||
slave.PSEL.value = 0
|
||||
slave.PENABLE.value = 0
|
||||
slave.PWRITE.value = 0
|
||||
_set_value(entry["inputs"]["PREADY"], index, 0)
|
||||
await Timer(1, units="ns")
|
||||
|
||||
for name, master in masters.items():
|
||||
if name != "reg3":
|
||||
assert int(master.PSEL.value) == 0, f"{name} should remain idle on read"
|
||||
# ------------------------------------------------------------------
|
||||
# Read phase
|
||||
# ------------------------------------------------------------------
|
||||
read_data = _read_pattern(address, config["data_width"])
|
||||
_set_value(entry["inputs"]["PRDATA"], index, read_data)
|
||||
_set_value(entry["inputs"]["PREADY"], index, 1)
|
||||
_set_value(entry["inputs"]["PSLVERR"], index, 0)
|
||||
|
||||
assert int(s_apb.PRDATA.value) == READ_DATA, "Read data should return from master"
|
||||
assert int(s_apb.PREADY.value) == 1, "Ready must follow selected master"
|
||||
assert int(s_apb.PSLVERR.value) == 0, "No error expected on successful read"
|
||||
slave.PADDR.value = address
|
||||
slave.PWRITE.value = 0
|
||||
slave.PSEL.value = 1
|
||||
slave.PENABLE.value = 1
|
||||
|
||||
# Back to idle
|
||||
s_apb.PSEL.value = 0
|
||||
s_apb.PENABLE.value = 0
|
||||
masters["reg3"].PREADY.value = 0
|
||||
await Timer(1, units="ns")
|
||||
await Timer(1, units="ns")
|
||||
|
||||
assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must assert PSEL for read"
|
||||
assert _get_int(entry["outputs"]["PWRITE"], index) == 0, f"{master_name} should deassert write for reads"
|
||||
assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive read address"
|
||||
|
||||
for other_name, other_idx in _all_index_pairs(masters):
|
||||
if other_name == master_name and other_idx == index:
|
||||
continue
|
||||
other_entry = masters[other_name]
|
||||
assert (
|
||||
_get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
|
||||
), f"{other_name}{other_idx} must stay idle during read of {txn['label']}"
|
||||
|
||||
assert int(slave.PRDATA.value) == read_data, "Slave should observe readback data from master"
|
||||
assert int(slave.PREADY.value) == 1, "Slave ready should follow responding master"
|
||||
assert int(slave.PSLVERR.value) == 0, "Read should complete without error"
|
||||
|
||||
# Reset to idle before progressing
|
||||
slave.PSEL.value = 0
|
||||
slave.PENABLE.value = 0
|
||||
_set_value(entry["inputs"]["PREADY"], index, 0)
|
||||
_set_value(entry["inputs"]["PRDATA"], index, 0)
|
||||
await Timer(1, units="ns")
|
||||
|
||||
@@ -1,7 +1,10 @@
|
||||
"""Pytest wrapper launching the APB4 cocotb smoke test."""
|
||||
"""Pytest wrapper launching the APB4 cocotb smoke tests."""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
import json
|
||||
from pathlib import Path
|
||||
|
||||
import logging
|
||||
import pytest
|
||||
|
||||
from peakrdl_busdecoder.cpuif.apb4.apb4_cpuif_flat import APB4CpuifFlat
|
||||
@@ -11,20 +14,25 @@ try: # pragma: no cover - optional dependency shim
|
||||
except ImportError: # pragma: no cover
|
||||
from cocotb_tools.runner import get_runner
|
||||
|
||||
from tests.cocotb_lib.utils import compile_rdl_and_export, get_verilog_sources
|
||||
from tests.cocotb_lib import RDL_CASES
|
||||
from tests.cocotb_lib.utils import get_verilog_sources, prepare_cpuif_case
|
||||
|
||||
|
||||
@pytest.mark.simulation
|
||||
@pytest.mark.verilator
|
||||
def test_apb4_smoke(tmp_path: Path) -> None:
|
||||
"""Compile the APB4 design and execute the cocotb smoke test."""
|
||||
@pytest.mark.parametrize(("rdl_file", "top_name"), RDL_CASES, ids=[case[1] for case in RDL_CASES])
|
||||
def test_apb4_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
|
||||
"""Compile each APB4 design variant and execute the cocotb smoke test."""
|
||||
repo_root = Path(__file__).resolve().parents[4]
|
||||
rdl_path = repo_root / "tests" / "cocotb_lib" / "rdl" / rdl_file
|
||||
build_root = tmp_path / top_name
|
||||
|
||||
module_path, package_path = compile_rdl_and_export(
|
||||
str(repo_root / "tests" / "cocotb_lib" / "multiple_reg.rdl"),
|
||||
"multi_reg",
|
||||
tmp_path,
|
||||
module_path, package_path, config = prepare_cpuif_case(
|
||||
str(rdl_path),
|
||||
top_name,
|
||||
build_root,
|
||||
cpuif_cls=APB4CpuifFlat,
|
||||
control_signal="PSEL",
|
||||
)
|
||||
|
||||
sources = get_verilog_sources(
|
||||
@@ -34,17 +42,39 @@ def test_apb4_smoke(tmp_path: Path) -> None:
|
||||
)
|
||||
|
||||
runner = get_runner("verilator")
|
||||
build_dir = tmp_path / "sim_build"
|
||||
sim_build = build_root / "sim_build"
|
||||
|
||||
try:
|
||||
runner.build(
|
||||
sources=sources,
|
||||
hdl_toplevel=module_path.stem,
|
||||
build_dir=sim_build,
|
||||
log_file=str(build_root / "build.log"),
|
||||
)
|
||||
except SystemExit as e:
|
||||
# Print build log on failure for easier debugging
|
||||
log_path = build_root / "build.log"
|
||||
if log_path.exists():
|
||||
logging.error("\n\n=== Build Log ===\n")
|
||||
logging.error(log_path.read_text())
|
||||
logging.error("\n=== End Build Log ===\n")
|
||||
if e.code != 0:
|
||||
raise
|
||||
|
||||
runner.build(
|
||||
sources=sources,
|
||||
hdl_toplevel=module_path.stem,
|
||||
build_dir=build_dir,
|
||||
)
|
||||
|
||||
runner.test(
|
||||
hdl_toplevel=module_path.stem,
|
||||
test_module="tests.cocotb.apb4.smoke.test_register_access",
|
||||
build_dir=build_dir,
|
||||
log_file=str(tmp_path / "sim.log"),
|
||||
)
|
||||
try:
|
||||
runner.test(
|
||||
hdl_toplevel=module_path.stem,
|
||||
test_module="tests.cocotb.apb4.smoke.test_register_access",
|
||||
build_dir=sim_build,
|
||||
log_file=str(build_root / "simulation.log"),
|
||||
extra_env={"RDL_TEST_CONFIG": json.dumps(config)},
|
||||
)
|
||||
except SystemExit as e:
|
||||
# Print simulation log on failure for easier debugging
|
||||
log_path = build_root / "simulation.log"
|
||||
if log_path.exists():
|
||||
logging.error("\n\n=== Simulation Log ===\n")
|
||||
logging.error(log_path.read_text())
|
||||
logging.error("\n=== End Simulation Log ===\n")
|
||||
if e.code != 0:
|
||||
raise
|
||||
|
||||
@@ -1,15 +1,19 @@
|
||||
"""AXI4-Lite smoke test ensuring address decode fanout works."""
|
||||
"""AXI4-Lite smoke test driven from SystemRDL-generated register maps."""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
import json
|
||||
import os
|
||||
from typing import Any, Iterable
|
||||
|
||||
import cocotb
|
||||
from cocotb.triggers import Timer
|
||||
|
||||
WRITE_ADDR = 0x4
|
||||
READ_ADDR = 0x8
|
||||
WRITE_DATA = 0x1357_9BDF
|
||||
READ_DATA = 0x2468_ACED
|
||||
|
||||
from tests.cocotb_lib.handle_utils import SignalHandle, resolve_handle
|
||||
|
||||
class _AxilSlaveShim:
|
||||
"""Accessor for AXI4-Lite slave ports on the DUT."""
|
||||
|
||||
def __init__(self, dut):
|
||||
prefix = "s_axil"
|
||||
self.AWREADY = getattr(dut, f"{prefix}_AWREADY")
|
||||
@@ -33,129 +37,177 @@ class _AxilSlaveShim:
|
||||
self.RRESP = getattr(dut, f"{prefix}_RRESP")
|
||||
|
||||
|
||||
class _AxilMasterShim:
|
||||
def __init__(self, dut, base: str):
|
||||
self.AWREADY = getattr(dut, f"{base}_AWREADY")
|
||||
self.AWVALID = getattr(dut, f"{base}_AWVALID")
|
||||
self.AWADDR = getattr(dut, f"{base}_AWADDR")
|
||||
self.AWPROT = getattr(dut, f"{base}_AWPROT")
|
||||
self.WREADY = getattr(dut, f"{base}_WREADY")
|
||||
self.WVALID = getattr(dut, f"{base}_WVALID")
|
||||
self.WDATA = getattr(dut, f"{base}_WDATA")
|
||||
self.WSTRB = getattr(dut, f"{base}_WSTRB")
|
||||
self.BREADY = getattr(dut, f"{base}_BREADY")
|
||||
self.BVALID = getattr(dut, f"{base}_BVALID")
|
||||
self.BRESP = getattr(dut, f"{base}_BRESP")
|
||||
self.ARREADY = getattr(dut, f"{base}_ARREADY")
|
||||
self.ARVALID = getattr(dut, f"{base}_ARVALID")
|
||||
self.ARADDR = getattr(dut, f"{base}_ARADDR")
|
||||
self.ARPROT = getattr(dut, f"{base}_ARPROT")
|
||||
self.RREADY = getattr(dut, f"{base}_RREADY")
|
||||
self.RVALID = getattr(dut, f"{base}_RVALID")
|
||||
self.RDATA = getattr(dut, f"{base}_RDATA")
|
||||
self.RRESP = getattr(dut, f"{base}_RRESP")
|
||||
def _load_config() -> dict[str, Any]:
|
||||
payload = os.environ.get("RDL_TEST_CONFIG")
|
||||
if payload is None:
|
||||
raise RuntimeError("RDL_TEST_CONFIG environment variable was not provided")
|
||||
return json.loads(payload)
|
||||
|
||||
|
||||
def _axil_slave(dut):
|
||||
return getattr(dut, "s_axil", None) or _AxilSlaveShim(dut)
|
||||
def _resolve(handle, indices: Iterable[int]):
|
||||
return resolve_handle(handle, indices)
|
||||
|
||||
|
||||
def _axil_master(dut, base: str):
|
||||
return getattr(dut, base, None) or _AxilMasterShim(dut, base)
|
||||
def _set_value(handle, indices: Iterable[int], value: int) -> None:
|
||||
_resolve(handle, indices).value = value
|
||||
|
||||
|
||||
def _get_int(handle, indices: Iterable[int]) -> int:
|
||||
return int(_resolve(handle, indices).value)
|
||||
|
||||
|
||||
def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dict[str, Any]]:
|
||||
table: dict[str, dict[str, Any]] = {}
|
||||
for master in masters_cfg:
|
||||
prefix = master["port_prefix"]
|
||||
entry = {
|
||||
"indices": [tuple(idx) for idx in master["indices"]] or [tuple()],
|
||||
"outputs": {
|
||||
"AWVALID": SignalHandle(dut, f"{prefix}_AWVALID"),
|
||||
"AWADDR": SignalHandle(dut, f"{prefix}_AWADDR"),
|
||||
"AWPROT": SignalHandle(dut, f"{prefix}_AWPROT"),
|
||||
"WVALID": SignalHandle(dut, f"{prefix}_WVALID"),
|
||||
"WDATA": SignalHandle(dut, f"{prefix}_WDATA"),
|
||||
"WSTRB": SignalHandle(dut, f"{prefix}_WSTRB"),
|
||||
"ARVALID": SignalHandle(dut, f"{prefix}_ARVALID"),
|
||||
"ARADDR": SignalHandle(dut, f"{prefix}_ARADDR"),
|
||||
"ARPROT": SignalHandle(dut, f"{prefix}_ARPROT"),
|
||||
},
|
||||
"inputs": {
|
||||
"AWREADY": SignalHandle(dut, f"{prefix}_AWREADY"),
|
||||
"WREADY": SignalHandle(dut, f"{prefix}_WREADY"),
|
||||
"BVALID": SignalHandle(dut, f"{prefix}_BVALID"),
|
||||
"BRESP": SignalHandle(dut, f"{prefix}_BRESP"),
|
||||
"ARREADY": SignalHandle(dut, f"{prefix}_ARREADY"),
|
||||
"RVALID": SignalHandle(dut, f"{prefix}_RVALID"),
|
||||
"RDATA": SignalHandle(dut, f"{prefix}_RDATA"),
|
||||
"RRESP": SignalHandle(dut, f"{prefix}_RRESP"),
|
||||
},
|
||||
}
|
||||
table[master["inst_name"]] = entry
|
||||
return table
|
||||
|
||||
|
||||
def _all_index_pairs(table: dict[str, dict[str, Any]]):
|
||||
for name, entry in table.items():
|
||||
for idx in entry["indices"]:
|
||||
yield name, idx
|
||||
|
||||
|
||||
def _write_pattern(address: int, width: int) -> int:
|
||||
mask = (1 << width) - 1
|
||||
return ((address * 0x3105) ^ 0x1357_9BDF) & mask
|
||||
|
||||
|
||||
def _read_pattern(address: int, width: int) -> int:
|
||||
mask = (1 << width) - 1
|
||||
return ((address ^ 0x2468_ACED) + width) & mask
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def test_axi4lite_read_write_paths(dut):
|
||||
"""Drive AXI4-Lite slave channels and validate master side wiring."""
|
||||
s_axil = _axil_slave(dut)
|
||||
masters = {
|
||||
"reg1": _axil_master(dut, "m_axil_reg1"),
|
||||
"reg2": _axil_master(dut, "m_axil_reg2"),
|
||||
"reg3": _axil_master(dut, "m_axil_reg3"),
|
||||
}
|
||||
async def test_axi4lite_address_decoding(dut) -> None:
|
||||
"""Stimulate AXI4-Lite slave channels and verify master port selection."""
|
||||
config = _load_config()
|
||||
slave = _AxilSlaveShim(dut)
|
||||
masters = _build_master_table(dut, config["masters"])
|
||||
|
||||
# Default slave-side inputs
|
||||
s_axil.AWVALID.value = 0
|
||||
s_axil.AWADDR.value = 0
|
||||
s_axil.AWPROT.value = 0
|
||||
s_axil.WVALID.value = 0
|
||||
s_axil.WDATA.value = 0
|
||||
s_axil.WSTRB.value = 0
|
||||
s_axil.BREADY.value = 0
|
||||
s_axil.ARVALID.value = 0
|
||||
s_axil.ARADDR.value = 0
|
||||
s_axil.ARPROT.value = 0
|
||||
s_axil.RREADY.value = 0
|
||||
slave.AWVALID.value = 0
|
||||
slave.AWADDR.value = 0
|
||||
slave.AWPROT.value = 0
|
||||
slave.WVALID.value = 0
|
||||
slave.WDATA.value = 0
|
||||
slave.WSTRB.value = 0
|
||||
slave.BREADY.value = 0
|
||||
slave.ARVALID.value = 0
|
||||
slave.ARADDR.value = 0
|
||||
slave.ARPROT.value = 0
|
||||
slave.RREADY.value = 0
|
||||
|
||||
for master in masters.values():
|
||||
master.AWREADY.value = 0
|
||||
master.WREADY.value = 0
|
||||
master.BVALID.value = 0
|
||||
master.BRESP.value = 0
|
||||
master.ARREADY.value = 0
|
||||
master.RVALID.value = 0
|
||||
master.RDATA.value = 0
|
||||
master.RRESP.value = 0
|
||||
for master_name, idx in _all_index_pairs(masters):
|
||||
entry = masters[master_name]
|
||||
_set_value(entry["inputs"]["AWREADY"], idx, 0)
|
||||
_set_value(entry["inputs"]["WREADY"], idx, 0)
|
||||
_set_value(entry["inputs"]["BVALID"], idx, 0)
|
||||
_set_value(entry["inputs"]["BRESP"], idx, 0)
|
||||
_set_value(entry["inputs"]["ARREADY"], idx, 0)
|
||||
_set_value(entry["inputs"]["RVALID"], idx, 0)
|
||||
_set_value(entry["inputs"]["RDATA"], idx, 0)
|
||||
_set_value(entry["inputs"]["RRESP"], idx, 0)
|
||||
|
||||
await Timer(1, units="ns")
|
||||
|
||||
# --------------------------------------------------------------
|
||||
# Write transaction targeting reg2
|
||||
# --------------------------------------------------------------
|
||||
s_axil.AWADDR.value = WRITE_ADDR
|
||||
s_axil.AWPROT.value = 0
|
||||
s_axil.AWVALID.value = 1
|
||||
s_axil.WDATA.value = WRITE_DATA
|
||||
s_axil.WSTRB.value = 0xF
|
||||
s_axil.WVALID.value = 1
|
||||
s_axil.BREADY.value = 1
|
||||
addr_mask = (1 << config["address_width"]) - 1
|
||||
strobe_mask = (1 << config["byte_width"]) - 1
|
||||
|
||||
await Timer(1, units="ns")
|
||||
for txn in config["transactions"]:
|
||||
master_name = txn["master"]
|
||||
index = tuple(txn["index"])
|
||||
entry = masters[master_name]
|
||||
|
||||
assert int(masters["reg2"].AWVALID.value) == 1, "reg2 AWVALID should follow slave"
|
||||
assert int(masters["reg2"].WVALID.value) == 1, "reg2 WVALID should follow slave"
|
||||
assert int(masters["reg2"].AWADDR.value) == WRITE_ADDR, "AWADDR should fan out"
|
||||
assert int(masters["reg2"].WDATA.value) == WRITE_DATA, "WDATA should fan out"
|
||||
assert int(masters["reg2"].WSTRB.value) == 0xF, "WSTRB should propagate"
|
||||
address = txn["address"] & addr_mask
|
||||
write_data = _write_pattern(address, config["data_width"])
|
||||
|
||||
for name, master in masters.items():
|
||||
if name != "reg2":
|
||||
assert int(master.AWVALID.value) == 0, f"{name} AWVALID should stay low"
|
||||
assert int(master.WVALID.value) == 0, f"{name} WVALID should stay low"
|
||||
slave.AWADDR.value = address
|
||||
slave.AWPROT.value = 0
|
||||
slave.AWVALID.value = 1
|
||||
slave.WDATA.value = write_data
|
||||
slave.WSTRB.value = strobe_mask
|
||||
slave.WVALID.value = 1
|
||||
slave.BREADY.value = 1
|
||||
|
||||
# Release write channel
|
||||
s_axil.AWVALID.value = 0
|
||||
s_axil.WVALID.value = 0
|
||||
s_axil.BREADY.value = 0
|
||||
await Timer(1, units="ns")
|
||||
await Timer(1, units="ns")
|
||||
|
||||
# --------------------------------------------------------------
|
||||
# Read transaction targeting reg3
|
||||
# --------------------------------------------------------------
|
||||
masters["reg3"].RVALID.value = 1
|
||||
masters["reg3"].RDATA.value = READ_DATA
|
||||
masters["reg3"].RRESP.value = 0
|
||||
assert _get_int(entry["outputs"]["AWVALID"], index) == 1, f"{master_name} should see AWVALID asserted"
|
||||
assert _get_int(entry["outputs"]["AWADDR"], index) == address, f"{master_name} must receive AWADDR"
|
||||
assert _get_int(entry["outputs"]["WVALID"], index) == 1, f"{master_name} should see WVALID asserted"
|
||||
assert _get_int(entry["outputs"]["WDATA"], index) == write_data, f"{master_name} must receive WDATA"
|
||||
assert _get_int(entry["outputs"]["WSTRB"], index) == strobe_mask, f"{master_name} must receive WSTRB"
|
||||
|
||||
s_axil.ARADDR.value = READ_ADDR
|
||||
s_axil.ARPROT.value = 0
|
||||
s_axil.ARVALID.value = 1
|
||||
s_axil.RREADY.value = 1
|
||||
for other_name, other_idx in _all_index_pairs(masters):
|
||||
if other_name == master_name and other_idx == index:
|
||||
continue
|
||||
other_entry = masters[other_name]
|
||||
assert (
|
||||
_get_int(other_entry["outputs"]["AWVALID"], other_idx) == 0
|
||||
), f"{other_name}{other_idx} AWVALID should remain low during {txn['label']}"
|
||||
assert (
|
||||
_get_int(other_entry["outputs"]["WVALID"], other_idx) == 0
|
||||
), f"{other_name}{other_idx} WVALID should remain low during {txn['label']}"
|
||||
|
||||
await Timer(1, units="ns")
|
||||
slave.AWVALID.value = 0
|
||||
slave.WVALID.value = 0
|
||||
slave.BREADY.value = 0
|
||||
await Timer(1, units="ns")
|
||||
|
||||
assert int(masters["reg3"].ARVALID.value) == 1, "reg3 ARVALID should follow slave"
|
||||
assert int(masters["reg3"].ARADDR.value) == READ_ADDR, "ARADDR should fan out"
|
||||
read_data = _read_pattern(address, config["data_width"])
|
||||
_set_value(entry["inputs"]["RVALID"], index, 1)
|
||||
_set_value(entry["inputs"]["RDATA"], index, read_data)
|
||||
_set_value(entry["inputs"]["RRESP"], index, 0)
|
||||
|
||||
for name, master in masters.items():
|
||||
if name != "reg3":
|
||||
assert int(master.ARVALID.value) == 0, f"{name} ARVALID should stay low"
|
||||
slave.ARADDR.value = address
|
||||
slave.ARPROT.value = 0
|
||||
slave.ARVALID.value = 1
|
||||
slave.RREADY.value = 1
|
||||
|
||||
assert int(s_axil.RVALID.value) == 1, "Slave should raise RVALID when master responds"
|
||||
assert int(s_axil.RDATA.value) == READ_DATA, "Read data should return to slave"
|
||||
assert int(s_axil.RRESP.value) == 0, "No error expected for read"
|
||||
await Timer(1, units="ns")
|
||||
|
||||
# Return to idle
|
||||
s_axil.ARVALID.value = 0
|
||||
s_axil.RREADY.value = 0
|
||||
masters["reg3"].RVALID.value = 0
|
||||
await Timer(1, units="ns")
|
||||
assert _get_int(entry["outputs"]["ARVALID"], index) == 1, f"{master_name} should assert ARVALID"
|
||||
assert _get_int(entry["outputs"]["ARADDR"], index) == address, f"{master_name} must receive ARADDR"
|
||||
|
||||
for other_name, other_idx in _all_index_pairs(masters):
|
||||
if other_name == master_name and other_idx == index:
|
||||
continue
|
||||
other_entry = masters[other_name]
|
||||
assert (
|
||||
_get_int(other_entry["outputs"]["ARVALID"], other_idx) == 0
|
||||
), f"{other_name}{other_idx} ARVALID should remain low during read of {txn['label']}"
|
||||
|
||||
assert int(slave.RVALID.value) == 1, "Slave should observe RVALID when master responds"
|
||||
assert int(slave.RDATA.value) == read_data, "Read data must fold back to slave"
|
||||
assert int(slave.RRESP.value) == 0, "Read response should indicate success"
|
||||
|
||||
slave.ARVALID.value = 0
|
||||
slave.RREADY.value = 0
|
||||
_set_value(entry["inputs"]["RVALID"], index, 0)
|
||||
_set_value(entry["inputs"]["RDATA"], index, 0)
|
||||
await Timer(1, units="ns")
|
||||
|
||||
@@ -1,5 +1,8 @@
|
||||
"""Pytest wrapper launching the AXI4-Lite cocotb smoke test."""
|
||||
"""Pytest wrapper launching the AXI4-Lite cocotb smoke tests."""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
import json
|
||||
from pathlib import Path
|
||||
|
||||
import pytest
|
||||
@@ -11,20 +14,25 @@ try: # pragma: no cover - optional dependency shim
|
||||
except ImportError: # pragma: no cover
|
||||
from cocotb_tools.runner import get_runner
|
||||
|
||||
from tests.cocotb_lib.utils import compile_rdl_and_export, get_verilog_sources
|
||||
from tests.cocotb_lib import RDL_CASES
|
||||
from tests.cocotb_lib.utils import get_verilog_sources, prepare_cpuif_case
|
||||
|
||||
|
||||
@pytest.mark.simulation
|
||||
@pytest.mark.verilator
|
||||
def test_axi4lite_smoke(tmp_path: Path) -> None:
|
||||
"""Compile the AXI4-Lite design and execute the cocotb smoke test."""
|
||||
@pytest.mark.parametrize(("rdl_file", "top_name"), RDL_CASES, ids=[case[1] for case in RDL_CASES])
|
||||
def test_axi4lite_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
|
||||
"""Compile each AXI4-Lite design variant and execute the cocotb smoke test."""
|
||||
repo_root = Path(__file__).resolve().parents[4]
|
||||
rdl_path = repo_root / "tests" / "cocotb_lib" / "rdl" / rdl_file
|
||||
build_root = tmp_path / top_name
|
||||
|
||||
module_path, package_path = compile_rdl_and_export(
|
||||
str(repo_root / "tests" / "cocotb_lib" / "multiple_reg.rdl"),
|
||||
"multi_reg",
|
||||
tmp_path,
|
||||
module_path, package_path, config = prepare_cpuif_case(
|
||||
str(rdl_path),
|
||||
top_name,
|
||||
build_root,
|
||||
cpuif_cls=AXI4LiteCpuifFlat,
|
||||
control_signal="AWVALID",
|
||||
)
|
||||
|
||||
sources = get_verilog_sources(
|
||||
@@ -34,17 +42,18 @@ def test_axi4lite_smoke(tmp_path: Path) -> None:
|
||||
)
|
||||
|
||||
runner = get_runner("verilator")
|
||||
build_dir = tmp_path / "sim_build"
|
||||
sim_build = build_root / "sim_build"
|
||||
|
||||
runner.build(
|
||||
sources=sources,
|
||||
hdl_toplevel=module_path.stem,
|
||||
build_dir=build_dir,
|
||||
build_dir=sim_build,
|
||||
)
|
||||
|
||||
runner.test(
|
||||
hdl_toplevel=module_path.stem,
|
||||
test_module="tests.cocotb.axi4lite.smoke.test_register_access",
|
||||
build_dir=build_dir,
|
||||
log_file=str(tmp_path / "sim.log"),
|
||||
build_dir=sim_build,
|
||||
log_file=str(build_root / "simulation.log"),
|
||||
extra_env={"RDL_TEST_CONFIG": json.dumps(config)},
|
||||
)
|
||||
|
||||
Reference in New Issue
Block a user