Tests/cocotb (#19)
* wip * reorg * update sv int * apb4 working * apb3 working * version bump + ignore runner warning * remove redundant check * adding log on failure * cleaning up verilator version issue * devcontainer * Fix missing libpython in GitHub Actions CI environment (#21) * Initial plan * Install libpython in GitHub Actions for cocotb tests Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: Copilot <198982749+Copilot@users.noreply.github.com>
This commit is contained in:
Arnav Sacheti
@@ -1,15 +1,19 @@
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"""APB3 smoke tests for generated multi-register design."""
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"""APB3 smoke tests generated from SystemRDL sources."""
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from __future__ import annotations
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import json
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import os
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from typing import Any, Iterable
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import cocotb
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from cocotb.triggers import Timer
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WRITE_ADDR = 0x0
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READ_ADDR = 0x8
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WRITE_DATA = 0xCAFEBABE
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READ_DATA = 0x0BAD_F00D
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from tests.cocotb_lib.handle_utils import SignalHandle, resolve_handle
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class _Apb3SlaveShim:
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"""Accessor for the APB3 slave signals on the DUT."""
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def __init__(self, dut):
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prefix = "s_apb"
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self.PSEL = getattr(dut, f"{prefix}_PSEL")
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@@ -22,102 +26,161 @@ class _Apb3SlaveShim:
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self.PSLVERR = getattr(dut, f"{prefix}_PSLVERR")
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class _Apb3MasterShim:
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def __init__(self, dut, base: str):
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self.PSEL = getattr(dut, f"{base}_PSEL")
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self.PENABLE = getattr(dut, f"{base}_PENABLE")
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self.PWRITE = getattr(dut, f"{base}_PWRITE")
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self.PADDR = getattr(dut, f"{base}_PADDR")
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self.PWDATA = getattr(dut, f"{base}_PWDATA")
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self.PRDATA = getattr(dut, f"{base}_PRDATA")
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self.PREADY = getattr(dut, f"{base}_PREADY")
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self.PSLVERR = getattr(dut, f"{base}_PSLVERR")
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def _load_config() -> dict[str, Any]:
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payload = os.environ.get("RDL_TEST_CONFIG")
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if payload is None:
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raise RuntimeError("RDL_TEST_CONFIG environment variable was not provided")
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return json.loads(payload)
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def _apb3_slave(dut):
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return getattr(dut, "s_apb", None) or _Apb3SlaveShim(dut)
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def _resolve(handle, indices: Iterable[int]):
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return resolve_handle(handle, indices)
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def _apb3_master(dut, base: str):
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return getattr(dut, base, None) or _Apb3MasterShim(dut, base)
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def _set_value(handle, indices: Iterable[int], value: int) -> None:
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_resolve(handle, indices).value = value
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def _get_int(handle, indices: Iterable[int]) -> int:
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return int(_resolve(handle, indices).value)
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def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dict[str, Any]]:
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table: dict[str, dict[str, Any]] = {}
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for master in masters_cfg:
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prefix = master["port_prefix"]
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entry = {
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"indices": [tuple(idx) for idx in master["indices"]] or [tuple()],
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"outputs": {
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"PSEL": SignalHandle(dut, f"{prefix}_PSEL"),
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"PENABLE": SignalHandle(dut, f"{prefix}_PENABLE"),
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"PWRITE": SignalHandle(dut, f"{prefix}_PWRITE"),
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"PADDR": SignalHandle(dut, f"{prefix}_PADDR"),
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"PWDATA": SignalHandle(dut, f"{prefix}_PWDATA"),
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},
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"inputs": {
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"PRDATA": SignalHandle(dut, f"{prefix}_PRDATA"),
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"PREADY": SignalHandle(dut, f"{prefix}_PREADY"),
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"PSLVERR": SignalHandle(dut, f"{prefix}_PSLVERR"),
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},
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}
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table[master["inst_name"]] = entry
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return table
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def _all_index_pairs(table: dict[str, dict[str, Any]]):
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for name, entry in table.items():
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for idx in entry["indices"]:
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yield name, idx
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def _write_pattern(address: int, width: int) -> int:
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mask = (1 << width) - 1
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return ((address * 0x2041) ^ 0xCAFEBABE) & mask
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def _read_pattern(address: int, width: int) -> int:
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mask = (1 << width) - 1
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return ((address ^ 0x0BAD_F00D) + width) & mask
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@cocotb.test()
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async def test_apb3_read_write_paths(dut):
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"""Exercise APB3 slave interface and observe master fanout."""
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s_apb = _apb3_slave(dut)
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masters = {
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"reg1": _apb3_master(dut, "m_apb_reg1"),
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"reg2": _apb3_master(dut, "m_apb_reg2"),
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"reg3": _apb3_master(dut, "m_apb_reg3"),
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}
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async def test_apb3_address_decoding(dut) -> None:
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"""Exercise the APB3 slave interface against sampled register addresses."""
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config = _load_config()
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slave = _Apb3SlaveShim(dut)
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masters = _build_master_table(dut, config["masters"])
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s_apb.PSEL.value = 0
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s_apb.PENABLE.value = 0
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s_apb.PWRITE.value = 0
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s_apb.PADDR.value = 0
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s_apb.PWDATA.value = 0
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slave.PSEL.value = 0
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slave.PENABLE.value = 0
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slave.PWRITE.value = 0
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slave.PADDR.value = 0
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slave.PWDATA.value = 0
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for master in masters.values():
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master.PRDATA.value = 0
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master.PREADY.value = 0
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master.PSLVERR.value = 0
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for master_name, idx in _all_index_pairs(masters):
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entry = masters[master_name]
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_set_value(entry["inputs"]["PRDATA"], idx, 0)
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_set_value(entry["inputs"]["PREADY"], idx, 0)
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_set_value(entry["inputs"]["PSLVERR"], idx, 0)
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await Timer(1, units="ns")
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# Write to reg1
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masters["reg1"].PREADY.value = 1
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s_apb.PADDR.value = WRITE_ADDR
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s_apb.PWDATA.value = WRITE_DATA
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s_apb.PWRITE.value = 1
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s_apb.PSEL.value = 1
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s_apb.PENABLE.value = 1
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addr_mask = (1 << config["address_width"]) - 1
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await Timer(1, units="ns")
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for txn in config["transactions"]:
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master_name = txn["master"]
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index = tuple(txn["index"])
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entry = masters[master_name]
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assert int(masters["reg1"].PSEL.value) == 1, "reg1 should be selected for write"
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assert int(masters["reg1"].PWRITE.value) == 1, "Write should propagate to master"
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assert int(masters["reg1"].PADDR.value) == WRITE_ADDR, "Address should reach selected master"
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assert int(masters["reg1"].PWDATA.value) == WRITE_DATA, "Write data should fan out"
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address = txn["address"] & addr_mask
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write_data = _write_pattern(address, config["data_width"])
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for name, master in masters.items():
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if name != "reg1":
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assert int(master.PSEL.value) == 0, f"{name} must idle during reg1 write"
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_set_value(entry["inputs"]["PREADY"], index, 1)
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_set_value(entry["inputs"]["PSLVERR"], index, 0)
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assert int(s_apb.PREADY.value) == 1, "Ready must reflect selected master"
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assert int(s_apb.PSLVERR.value) == 0, "Write should not signal error"
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slave.PADDR.value = address
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slave.PWDATA.value = write_data
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slave.PWRITE.value = 1
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slave.PSEL.value = 1
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slave.PENABLE.value = 1
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s_apb.PSEL.value = 0
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s_apb.PENABLE.value = 0
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s_apb.PWRITE.value = 0
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masters["reg1"].PREADY.value = 0
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await Timer(1, units="ns")
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await Timer(1, units="ns")
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# Read from reg3
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masters["reg3"].PRDATA.value = READ_DATA
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masters["reg3"].PREADY.value = 1
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masters["reg3"].PSLVERR.value = 0
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assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
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assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write direction"
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assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive write address"
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assert _get_int(entry["outputs"]["PWDATA"], index) == write_data, f"{master_name} must receive write data"
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s_apb.PADDR.value = READ_ADDR
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s_apb.PSEL.value = 1
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s_apb.PENABLE.value = 1
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s_apb.PWRITE.value = 0
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for other_name, other_idx in _all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert (
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_get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
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), f"{other_name}{other_idx} should remain idle during {txn['label']}"
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await Timer(1, units="ns")
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assert int(slave.PREADY.value) == 1, "Slave ready should mirror selected master"
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assert int(slave.PSLVERR.value) == 0, "Write should complete without error"
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assert int(masters["reg3"].PSEL.value) == 1, "reg3 should be selected for read"
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assert int(masters["reg3"].PWRITE.value) == 0, "Read should clear write"
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assert int(masters["reg3"].PADDR.value) == READ_ADDR, "Address should reach read target"
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slave.PSEL.value = 0
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slave.PENABLE.value = 0
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slave.PWRITE.value = 0
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_set_value(entry["inputs"]["PREADY"], index, 0)
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await Timer(1, units="ns")
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for name, master in masters.items():
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if name != "reg3":
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assert int(master.PSEL.value) == 0, f"{name} must idle during reg3 read"
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# ------------------------------------------------------------------
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# Read phase
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# ------------------------------------------------------------------
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read_data = _read_pattern(address, config["data_width"])
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_set_value(entry["inputs"]["PRDATA"], index, read_data)
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_set_value(entry["inputs"]["PREADY"], index, 1)
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_set_value(entry["inputs"]["PSLVERR"], index, 0)
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assert int(s_apb.PRDATA.value) == READ_DATA, "Read data should return to slave"
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assert int(s_apb.PREADY.value) == 1, "Read should acknowledge"
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assert int(s_apb.PSLVERR.value) == 0, "Read should not signal error"
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slave.PADDR.value = address
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slave.PWRITE.value = 0
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slave.PSEL.value = 1
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slave.PENABLE.value = 1
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s_apb.PSEL.value = 0
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s_apb.PENABLE.value = 0
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masters["reg3"].PREADY.value = 0
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await Timer(1, units="ns")
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await Timer(1, units="ns")
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assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must assert PSEL for read"
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assert _get_int(entry["outputs"]["PWRITE"], index) == 0, f"{master_name} should clear write during read"
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assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive read address"
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for other_name, other_idx in _all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert (
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_get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
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), f"{other_name}{other_idx} must stay idle during read of {txn['label']}"
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assert int(slave.PRDATA.value) == read_data, "Read data should propagate back to the slave"
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assert int(slave.PREADY.value) == 1, "Slave ready should acknowledge the read"
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assert int(slave.PSLVERR.value) == 0, "Read should not signal an error"
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slave.PSEL.value = 0
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slave.PENABLE.value = 0
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_set_value(entry["inputs"]["PREADY"], index, 0)
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_set_value(entry["inputs"]["PRDATA"], index, 0)
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await Timer(1, units="ns")
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