Tests/cocotb (#19)
* wip * reorg * update sv int * apb4 working * apb3 working * version bump + ignore runner warning * remove redundant check * adding log on failure * cleaning up verilator version issue * devcontainer * Fix missing libpython in GitHub Actions CI environment (#21) * Initial plan * Install libpython in GitHub Actions for cocotb tests Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: Copilot <198982749+Copilot@users.noreply.github.com>
This commit is contained in:
Arnav Sacheti
@@ -1,15 +1,19 @@
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"""AXI4-Lite smoke test ensuring address decode fanout works."""
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"""AXI4-Lite smoke test driven from SystemRDL-generated register maps."""
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from __future__ import annotations
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import json
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import os
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from typing import Any, Iterable
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import cocotb
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from cocotb.triggers import Timer
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WRITE_ADDR = 0x4
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READ_ADDR = 0x8
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WRITE_DATA = 0x1357_9BDF
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READ_DATA = 0x2468_ACED
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from tests.cocotb_lib.handle_utils import SignalHandle, resolve_handle
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class _AxilSlaveShim:
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"""Accessor for AXI4-Lite slave ports on the DUT."""
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def __init__(self, dut):
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prefix = "s_axil"
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self.AWREADY = getattr(dut, f"{prefix}_AWREADY")
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@@ -33,129 +37,177 @@ class _AxilSlaveShim:
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self.RRESP = getattr(dut, f"{prefix}_RRESP")
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class _AxilMasterShim:
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def __init__(self, dut, base: str):
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self.AWREADY = getattr(dut, f"{base}_AWREADY")
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self.AWVALID = getattr(dut, f"{base}_AWVALID")
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self.AWADDR = getattr(dut, f"{base}_AWADDR")
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self.AWPROT = getattr(dut, f"{base}_AWPROT")
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self.WREADY = getattr(dut, f"{base}_WREADY")
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self.WVALID = getattr(dut, f"{base}_WVALID")
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self.WDATA = getattr(dut, f"{base}_WDATA")
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self.WSTRB = getattr(dut, f"{base}_WSTRB")
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self.BREADY = getattr(dut, f"{base}_BREADY")
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self.BVALID = getattr(dut, f"{base}_BVALID")
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self.BRESP = getattr(dut, f"{base}_BRESP")
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self.ARREADY = getattr(dut, f"{base}_ARREADY")
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self.ARVALID = getattr(dut, f"{base}_ARVALID")
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self.ARADDR = getattr(dut, f"{base}_ARADDR")
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self.ARPROT = getattr(dut, f"{base}_ARPROT")
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self.RREADY = getattr(dut, f"{base}_RREADY")
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self.RVALID = getattr(dut, f"{base}_RVALID")
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self.RDATA = getattr(dut, f"{base}_RDATA")
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self.RRESP = getattr(dut, f"{base}_RRESP")
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def _load_config() -> dict[str, Any]:
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payload = os.environ.get("RDL_TEST_CONFIG")
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if payload is None:
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raise RuntimeError("RDL_TEST_CONFIG environment variable was not provided")
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return json.loads(payload)
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def _axil_slave(dut):
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return getattr(dut, "s_axil", None) or _AxilSlaveShim(dut)
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def _resolve(handle, indices: Iterable[int]):
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return resolve_handle(handle, indices)
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def _axil_master(dut, base: str):
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return getattr(dut, base, None) or _AxilMasterShim(dut, base)
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def _set_value(handle, indices: Iterable[int], value: int) -> None:
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_resolve(handle, indices).value = value
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def _get_int(handle, indices: Iterable[int]) -> int:
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return int(_resolve(handle, indices).value)
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def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dict[str, Any]]:
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table: dict[str, dict[str, Any]] = {}
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for master in masters_cfg:
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prefix = master["port_prefix"]
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entry = {
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"indices": [tuple(idx) for idx in master["indices"]] or [tuple()],
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"outputs": {
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"AWVALID": SignalHandle(dut, f"{prefix}_AWVALID"),
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"AWADDR": SignalHandle(dut, f"{prefix}_AWADDR"),
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"AWPROT": SignalHandle(dut, f"{prefix}_AWPROT"),
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"WVALID": SignalHandle(dut, f"{prefix}_WVALID"),
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"WDATA": SignalHandle(dut, f"{prefix}_WDATA"),
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"WSTRB": SignalHandle(dut, f"{prefix}_WSTRB"),
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"ARVALID": SignalHandle(dut, f"{prefix}_ARVALID"),
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"ARADDR": SignalHandle(dut, f"{prefix}_ARADDR"),
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"ARPROT": SignalHandle(dut, f"{prefix}_ARPROT"),
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},
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"inputs": {
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"AWREADY": SignalHandle(dut, f"{prefix}_AWREADY"),
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"WREADY": SignalHandle(dut, f"{prefix}_WREADY"),
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"BVALID": SignalHandle(dut, f"{prefix}_BVALID"),
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"BRESP": SignalHandle(dut, f"{prefix}_BRESP"),
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"ARREADY": SignalHandle(dut, f"{prefix}_ARREADY"),
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"RVALID": SignalHandle(dut, f"{prefix}_RVALID"),
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"RDATA": SignalHandle(dut, f"{prefix}_RDATA"),
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"RRESP": SignalHandle(dut, f"{prefix}_RRESP"),
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},
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}
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table[master["inst_name"]] = entry
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return table
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def _all_index_pairs(table: dict[str, dict[str, Any]]):
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for name, entry in table.items():
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for idx in entry["indices"]:
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yield name, idx
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def _write_pattern(address: int, width: int) -> int:
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mask = (1 << width) - 1
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return ((address * 0x3105) ^ 0x1357_9BDF) & mask
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def _read_pattern(address: int, width: int) -> int:
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mask = (1 << width) - 1
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return ((address ^ 0x2468_ACED) + width) & mask
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@cocotb.test()
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async def test_axi4lite_read_write_paths(dut):
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"""Drive AXI4-Lite slave channels and validate master side wiring."""
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s_axil = _axil_slave(dut)
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masters = {
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"reg1": _axil_master(dut, "m_axil_reg1"),
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"reg2": _axil_master(dut, "m_axil_reg2"),
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"reg3": _axil_master(dut, "m_axil_reg3"),
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}
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async def test_axi4lite_address_decoding(dut) -> None:
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"""Stimulate AXI4-Lite slave channels and verify master port selection."""
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config = _load_config()
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slave = _AxilSlaveShim(dut)
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masters = _build_master_table(dut, config["masters"])
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# Default slave-side inputs
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s_axil.AWVALID.value = 0
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s_axil.AWADDR.value = 0
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s_axil.AWPROT.value = 0
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s_axil.WVALID.value = 0
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s_axil.WDATA.value = 0
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s_axil.WSTRB.value = 0
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s_axil.BREADY.value = 0
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s_axil.ARVALID.value = 0
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s_axil.ARADDR.value = 0
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s_axil.ARPROT.value = 0
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s_axil.RREADY.value = 0
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slave.AWVALID.value = 0
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slave.AWADDR.value = 0
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slave.AWPROT.value = 0
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slave.WVALID.value = 0
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slave.WDATA.value = 0
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slave.WSTRB.value = 0
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slave.BREADY.value = 0
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slave.ARVALID.value = 0
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slave.ARADDR.value = 0
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slave.ARPROT.value = 0
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slave.RREADY.value = 0
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for master in masters.values():
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master.AWREADY.value = 0
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master.WREADY.value = 0
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master.BVALID.value = 0
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master.BRESP.value = 0
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master.ARREADY.value = 0
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master.RVALID.value = 0
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master.RDATA.value = 0
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master.RRESP.value = 0
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for master_name, idx in _all_index_pairs(masters):
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entry = masters[master_name]
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_set_value(entry["inputs"]["AWREADY"], idx, 0)
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_set_value(entry["inputs"]["WREADY"], idx, 0)
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_set_value(entry["inputs"]["BVALID"], idx, 0)
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_set_value(entry["inputs"]["BRESP"], idx, 0)
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_set_value(entry["inputs"]["ARREADY"], idx, 0)
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_set_value(entry["inputs"]["RVALID"], idx, 0)
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_set_value(entry["inputs"]["RDATA"], idx, 0)
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_set_value(entry["inputs"]["RRESP"], idx, 0)
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await Timer(1, units="ns")
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# --------------------------------------------------------------
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# Write transaction targeting reg2
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# --------------------------------------------------------------
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s_axil.AWADDR.value = WRITE_ADDR
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s_axil.AWPROT.value = 0
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s_axil.AWVALID.value = 1
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s_axil.WDATA.value = WRITE_DATA
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s_axil.WSTRB.value = 0xF
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s_axil.WVALID.value = 1
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s_axil.BREADY.value = 1
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addr_mask = (1 << config["address_width"]) - 1
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strobe_mask = (1 << config["byte_width"]) - 1
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await Timer(1, units="ns")
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for txn in config["transactions"]:
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master_name = txn["master"]
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index = tuple(txn["index"])
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entry = masters[master_name]
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assert int(masters["reg2"].AWVALID.value) == 1, "reg2 AWVALID should follow slave"
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assert int(masters["reg2"].WVALID.value) == 1, "reg2 WVALID should follow slave"
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assert int(masters["reg2"].AWADDR.value) == WRITE_ADDR, "AWADDR should fan out"
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assert int(masters["reg2"].WDATA.value) == WRITE_DATA, "WDATA should fan out"
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assert int(masters["reg2"].WSTRB.value) == 0xF, "WSTRB should propagate"
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address = txn["address"] & addr_mask
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write_data = _write_pattern(address, config["data_width"])
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for name, master in masters.items():
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if name != "reg2":
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assert int(master.AWVALID.value) == 0, f"{name} AWVALID should stay low"
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assert int(master.WVALID.value) == 0, f"{name} WVALID should stay low"
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slave.AWADDR.value = address
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slave.AWPROT.value = 0
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slave.AWVALID.value = 1
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slave.WDATA.value = write_data
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slave.WSTRB.value = strobe_mask
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slave.WVALID.value = 1
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slave.BREADY.value = 1
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# Release write channel
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s_axil.AWVALID.value = 0
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s_axil.WVALID.value = 0
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s_axil.BREADY.value = 0
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await Timer(1, units="ns")
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await Timer(1, units="ns")
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# --------------------------------------------------------------
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# Read transaction targeting reg3
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# --------------------------------------------------------------
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masters["reg3"].RVALID.value = 1
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masters["reg3"].RDATA.value = READ_DATA
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masters["reg3"].RRESP.value = 0
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assert _get_int(entry["outputs"]["AWVALID"], index) == 1, f"{master_name} should see AWVALID asserted"
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assert _get_int(entry["outputs"]["AWADDR"], index) == address, f"{master_name} must receive AWADDR"
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assert _get_int(entry["outputs"]["WVALID"], index) == 1, f"{master_name} should see WVALID asserted"
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assert _get_int(entry["outputs"]["WDATA"], index) == write_data, f"{master_name} must receive WDATA"
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assert _get_int(entry["outputs"]["WSTRB"], index) == strobe_mask, f"{master_name} must receive WSTRB"
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s_axil.ARADDR.value = READ_ADDR
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s_axil.ARPROT.value = 0
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s_axil.ARVALID.value = 1
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s_axil.RREADY.value = 1
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for other_name, other_idx in _all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert (
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_get_int(other_entry["outputs"]["AWVALID"], other_idx) == 0
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), f"{other_name}{other_idx} AWVALID should remain low during {txn['label']}"
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assert (
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_get_int(other_entry["outputs"]["WVALID"], other_idx) == 0
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), f"{other_name}{other_idx} WVALID should remain low during {txn['label']}"
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await Timer(1, units="ns")
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slave.AWVALID.value = 0
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slave.WVALID.value = 0
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slave.BREADY.value = 0
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await Timer(1, units="ns")
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assert int(masters["reg3"].ARVALID.value) == 1, "reg3 ARVALID should follow slave"
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assert int(masters["reg3"].ARADDR.value) == READ_ADDR, "ARADDR should fan out"
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read_data = _read_pattern(address, config["data_width"])
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_set_value(entry["inputs"]["RVALID"], index, 1)
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_set_value(entry["inputs"]["RDATA"], index, read_data)
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_set_value(entry["inputs"]["RRESP"], index, 0)
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for name, master in masters.items():
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if name != "reg3":
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assert int(master.ARVALID.value) == 0, f"{name} ARVALID should stay low"
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slave.ARADDR.value = address
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slave.ARPROT.value = 0
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slave.ARVALID.value = 1
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slave.RREADY.value = 1
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assert int(s_axil.RVALID.value) == 1, "Slave should raise RVALID when master responds"
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assert int(s_axil.RDATA.value) == READ_DATA, "Read data should return to slave"
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assert int(s_axil.RRESP.value) == 0, "No error expected for read"
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await Timer(1, units="ns")
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# Return to idle
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s_axil.ARVALID.value = 0
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s_axil.RREADY.value = 0
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masters["reg3"].RVALID.value = 0
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await Timer(1, units="ns")
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assert _get_int(entry["outputs"]["ARVALID"], index) == 1, f"{master_name} should assert ARVALID"
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assert _get_int(entry["outputs"]["ARADDR"], index) == address, f"{master_name} must receive ARADDR"
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for other_name, other_idx in _all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert (
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_get_int(other_entry["outputs"]["ARVALID"], other_idx) == 0
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), f"{other_name}{other_idx} ARVALID should remain low during read of {txn['label']}"
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assert int(slave.RVALID.value) == 1, "Slave should observe RVALID when master responds"
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assert int(slave.RDATA.value) == read_data, "Read data must fold back to slave"
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assert int(slave.RRESP.value) == 0, "Read response should indicate success"
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slave.ARVALID.value = 0
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slave.RREADY.value = 0
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_set_value(entry["inputs"]["RVALID"], index, 0)
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_set_value(entry["inputs"]["RDATA"], index, 0)
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await Timer(1, units="ns")
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