bslathi19/PeakRDL-BusDecoder
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Gate assertions behind "PEAKRDL_ASSERTIONS define"

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Byron Lathi
2025-11-22 16:34:52 -08:00
parent b16eb33ee1
commit b0db1f60e4
3 changed files with 6 additions and 0 deletions
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2
src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
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@@ -6,9 +6,11 @@
assert_bad_data_width: assert($bits({{cpuif.signal("PWDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH) assert_bad_data_width: assert($bits({{cpuif.signal("PWDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("PWDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH); else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("PWDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
end end
`ifdef PEAKRDL_ASSERTIONS
assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("PSEL")}} && {{cpuif.signal("PWRITE")}} |-> ##1 ({{cpuif.signal("PREADY")}} || {{cpuif.signal("PSLVERR")}})) assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("PSEL")}} && {{cpuif.signal("PWRITE")}} |-> ##1 ({{cpuif.signal("PREADY")}} || {{cpuif.signal("PSLVERR")}}))
else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded"); else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
`endif `endif
`endif
{%- endif %} {%- endif %}
assign cpuif_req = {{cpuif.signal("PSEL")}}; assign cpuif_req = {{cpuif.signal("PSEL")}};

2
src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_tmpl.sv
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@@ -15,6 +15,7 @@
$bits({{cpuif.signal("WDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH); $bits({{cpuif.signal("WDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
end end
`ifdef PEAKRDL_ASSERTIONS
// Simple handshake sanity (one-cycle implication; relax/adjust as needed) // Simple handshake sanity (one-cycle implication; relax/adjust as needed)
assert_rd_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}}) assert_rd_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}})
{{cpuif.signal("RVALID")}} |-> (^{{cpuif.signal("RRESP")}} !== 1'bx)) {{cpuif.signal("RVALID")}} |-> (^{{cpuif.signal("RRESP")}} !== 1'bx))
@@ -24,6 +25,7 @@
{{cpuif.signal("BVALID")}} |-> (^{{cpuif.signal("BRESP")}} !== 1'bx)) {{cpuif.signal("BVALID")}} |-> (^{{cpuif.signal("BRESP")}} !== 1'bx))
else $error("BRESP must be a legal AXI response when BVALID is high"); else $error("BRESP must be a legal AXI response when BVALID is high");
`endif `endif
`endif
{% endif -%} {% endif -%}

2
src/peakrdl_busdecoder/cpuif/taxi_apb/taxi_apb_tmpl.sv
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@@ -6,9 +6,11 @@
assert_bad_data_width: assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH) assert_bad_data_width: assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("pwdata")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH); else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("pwdata")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
end end
`ifdef PEAKRDL_ASSERTIONS
assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("psel")}} && {{cpuif.signal("pwrite")}} |-> ##1 ({{cpuif.signal("pready")}} || {{cpuif.signal("pslverr")}})) assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("psel")}} && {{cpuif.signal("pwrite")}} |-> ##1 ({{cpuif.signal("pready")}} || {{cpuif.signal("pslverr")}}))
else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded"); else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
`endif `endif
`endif
{%- endif %} {%- endif %}
assign cpuif_req = {{cpuif.signal("psel")}}; assign cpuif_req = {{cpuif.signal("psel")}};