Refactor tests (better grouping + cocotb support) (#15)

* initial refactor

* fix cocotb tests

* fix typecheck

* install verilator

hdl-src/apb3_intf.sv

@@ -2,6 +2,10 @@ interface apb3_intf #(
     parameter DATA_WIDTH = 32,
     parameter ADDR_WIDTH = 32
 );
+    // Clocking
+    logic PCLK;
+    logic PRESETn;
+
     // Command
     logic PSEL;
     logic PENABLE;
@@ -15,6 +19,9 @@ interface apb3_intf #(
     logic PSLVERR;
 
     modport master (
+        input PCLK,
+        input PRESETn,
+
         output PSEL,
         output PENABLE,
         output PWRITE,
@@ -27,6 +34,9 @@ interface apb3_intf #(
     );
 
     modport slave (
+        input PCLK,
+        input PRESETn,
+
         input PSEL,
         input PENABLE,
         input PWRITE,

hdl-src/apb4_intf.sv

@@ -2,6 +2,10 @@ interface apb4_intf #(
     parameter DATA_WIDTH = 32,
     parameter ADDR_WIDTH = 32
 );
+    // Clocking
+    logic PCLK;
+    logic PRESETn;
+
     // Command
     logic PSEL;
     logic PENABLE;
@@ -17,6 +21,9 @@ interface apb4_intf #(
     logic PSLVERR;
 
     modport master (
+        input PCLK,
+        input PRESETn,
+
         output PSEL,
         output PENABLE,
         output PWRITE,
@@ -31,6 +38,9 @@ interface apb4_intf #(
     );
 
     modport slave (
+        input PCLK,
+        input PRESETn,
+
         input PSEL,
         input PENABLE,
         input PWRITE,

hdl-src/axi4lite_intf.sv

@@ -2,6 +2,9 @@ interface axi4lite_intf #(
     parameter DATA_WIDTH = 32,
     parameter ADDR_WIDTH = 32
 );
+    logic ACLK;
+    logic ARESETn;
+
     logic AWREADY;
     logic AWVALID;
     logic [ADDR_WIDTH-1:0] AWADDR;
@@ -27,6 +30,9 @@ interface axi4lite_intf #(
     logic [1:0] RRESP;
 
     modport master (
+        input ACLK,
+        input ARESETn,
+
         input AWREADY,
         output AWVALID,
         output AWADDR,
@@ -53,15 +59,18 @@ interface axi4lite_intf #(
     );
 
     modport slave (
+        input ACLK,
+        input ARESETn,
+
         output AWREADY,
-        // input AWVALID,
-        // input AWADDR,
+        input AWVALID,
+        input AWADDR,
         input AWPROT,
 
         output WREADY,
-        // input WVALID,
-        // input WDATA,
-        // input WSTRB,
+        input WVALID,
+        input WDATA,
+        input WSTRB,
 
         input BREADY,
         output BVALID,
@@ -73,8 +82,8 @@ interface axi4lite_intf #(
         input ARPROT,
 
         input RREADY,
-        // output RVALID,
-        // output RDATA,
-        // output RRESP
+        output RVALID,
+        output RDATA,
+        output RRESP
     );
 endinterface