Refactor tests (better grouping + cocotb support) (#15)

* initial refactor

* fix cocotb tests

* fix typecheck

* install verilator
This commit is contained in:
Arnav Sacheti
2025-10-26 17:56:35 -07:00
committed by GitHub
parent 93276ff616
commit b1f1bf983a
66 changed files with 1734 additions and 2963 deletions

View File

@@ -12,14 +12,14 @@ class APB3CpuifFlat(BaseCpuif):
return [
f"input logic {self.signal('PCLK', child)}",
f"input logic {self.signal('PRESETn', child)}",
f"input logic {self.signal('PSELx', child)}",
f"input logic {self.signal('PENABLE', child)}",
f"input logic {self.signal('PWRITE', child)}",
f"input logic [{self.addr_width - 1}:0] {self.signal('PADDR', child)}",
f"input logic [{self.data_width - 1}:0] {self.signal('PWDATA', child)}",
f"output logic [{self.data_width - 1}:0] {self.signal('PRDATA', child)}",
f"output logic {self.signal('PREADY', child)}",
f"output logic {self.signal('PSLVERR', child)}",
f"output logic {self.signal('PSELx', child)}",
f"output logic {self.signal('PENABLE', child)}",
f"output logic {self.signal('PWRITE', child)}",
f"output logic [{self.addr_width - 1}:0] {self.signal('PADDR', child)}",
f"output logic [{self.data_width - 1}:0] {self.signal('PWDATA', child)}",
f"input logic [{self.data_width - 1}:0] {self.signal('PRDATA', child)}",
f"input logic {self.signal('PREADY', child)}",
f"input logic {self.signal('PSLVERR', child)}",
]
@property
@@ -48,9 +48,10 @@ class APB3CpuifFlat(BaseCpuif):
node: AddressableNode | None = None,
idx: str | int | None = None,
) -> str:
mapped_signal = "PSELx" if signal == "PSEL" else signal
if node is None:
# Node is none, so this is a slave signal
return f"s_apb_{signal}"
return f"s_apb_{mapped_signal}"
# Master signal
base = f"m_apb_{node.inst_name}"
@@ -58,12 +59,12 @@ class APB3CpuifFlat(BaseCpuif):
# Not an array or an unrolled element
if node.current_idx is not None:
# This is a specific instance of an unrolled array
return f"{base}_{signal}_{'_'.join(map(str, node.current_idx))}"
return f"{base}_{signal}"
return f"{base}_{mapped_signal}_{'_'.join(map(str, node.current_idx))}"
return f"{base}_{mapped_signal}"
# Is an array
if idx is not None:
return f"{base}_{signal}[{idx}]"
return f"{base}_{signal}[N_{node.inst_name.upper()}S]"
return f"{base}_{mapped_signal}[{idx}]"
return f"{base}_{mapped_signal}[N_{node.inst_name.upper()}S]"
def fanout(self, node: AddressableNode) -> str:
fanout: dict[str, str] = {}