Refactor tests (better grouping + cocotb support) (#15)
* initial refactor * fix cocotb tests * fix typecheck * install verilator
This commit is contained in:
Arnav Sacheti
@@ -2,94 +2,91 @@ from typing import overload
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from systemrdl.node import AddressableNode
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from ...utils import get_indexed_path
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from ..base_cpuif import BaseCpuif
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from .axi4_lite_cpuif import AXI4LiteCpuif
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class AXI4LiteCpuifFlat(BaseCpuif):
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class AXI4LiteCpuifFlat(AXI4LiteCpuif):
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"""Verilator-friendly variant that flattens the AXI4-Lite interface ports."""
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template_path = "axi4lite_tmpl.sv"
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is_interface = True
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is_interface = False
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def _port_declaration(self, child: AddressableNode) -> str:
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base = f"axi4lite_intf.master m_axil_{child.inst_name}"
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# When unrolled, current_idx is set - append it to the name
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if child.current_idx is not None:
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base = f"{base}_{'_'.join(map(str, child.current_idx))}"
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# Only add array dimensions if this should be treated as an array
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if self.check_is_array(child):
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assert child.array_dimensions is not None
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return f"{base} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
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return base
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def _port_declaration(self, child: AddressableNode) -> list[str]:
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return [
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f"input logic {self.signal('AWREADY', child)}",
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f"output logic {self.signal('AWVALID', child)}",
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f"output logic [{self.addr_width - 1}:0] {self.signal('AWADDR', child)}",
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f"output logic [2:0] {self.signal('AWPROT', child)}",
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f"input logic {self.signal('WREADY', child)}",
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f"output logic {self.signal('WVALID', child)}",
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f"output logic [{self.data_width - 1}:0] {self.signal('WDATA', child)}",
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f"output logic [{self.data_width_bytes - 1}:0] {self.signal('WSTRB', child)}",
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f"output logic {self.signal('BREADY', child)}",
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f"input logic {self.signal('BVALID', child)}",
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f"input logic [1:0] {self.signal('BRESP', child)}",
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f"input logic {self.signal('ARREADY', child)}",
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f"output logic {self.signal('ARVALID', child)}",
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f"output logic [{self.addr_width - 1}:0] {self.signal('ARADDR', child)}",
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f"output logic [2:0] {self.signal('ARPROT', child)}",
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f"output logic {self.signal('RREADY', child)}",
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f"input logic {self.signal('RVALID', child)}",
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f"input logic [{self.data_width - 1}:0] {self.signal('RDATA', child)}",
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f"input logic [1:0] {self.signal('RRESP', child)}",
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]
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@property
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def port_declaration(self) -> str:
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"""Returns the port declaration for the AXI4-Lite interface."""
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slave_ports: list[str] = ["axi4lite_intf.slave s_axil"]
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master_ports: list[str] = list(map(self._port_declaration, self.addressable_children))
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slave_ports: list[str] = [
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f"input logic {self.signal('ACLK')}",
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f"input logic {self.signal('ARESETn')}",
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f"output logic {self.signal('AWREADY')}",
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f"input logic {self.signal('AWVALID')}",
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f"input logic [{self.addr_width - 1}:0] {self.signal('AWADDR')}",
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f"input logic [2:0] {self.signal('AWPROT')}",
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f"output logic {self.signal('WREADY')}",
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f"input logic {self.signal('WVALID')}",
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f"input logic [{self.data_width - 1}:0] {self.signal('WDATA')}",
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f"input logic [{self.data_width_bytes - 1}:0] {self.signal('WSTRB')}",
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f"input logic {self.signal('BREADY')}",
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f"output logic {self.signal('BVALID')}",
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f"output logic [1:0] {self.signal('BRESP')}",
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f"output logic {self.signal('ARREADY')}",
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f"input logic {self.signal('ARVALID')}",
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f"input logic [{self.addr_width - 1}:0] {self.signal('ARADDR')}",
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f"input logic [2:0] {self.signal('ARPROT')}",
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f"input logic {self.signal('RREADY')}",
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f"output logic {self.signal('RVALID')}",
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f"output logic [{self.data_width - 1}:0] {self.signal('RDATA')}",
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f"output logic [1:0] {self.signal('RRESP')}",
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]
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master_ports: list[str] = []
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for child in self.addressable_children:
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master_ports.extend(self._port_declaration(child))
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return ",\n".join(slave_ports + master_ports)
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@overload
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def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
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@overload
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def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
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def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
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if node is None or indexer is None:
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# Node is none, so this is a slave signal
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return f"s_axil.{signal}"
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def signal(self, signal: str, node: AddressableNode, indexer: str | None = None) -> str: ...
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# Master signal
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return f"m_axil_{get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)}.{signal}"
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def fanout(self, node: AddressableNode) -> str:
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fanout: dict[str, str] = {}
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wr_sel = f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
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rd_sel = f"cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
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# Write address channel
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fanout[self.signal("AWVALID", node, "gi")] = wr_sel
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fanout[self.signal("AWADDR", node, "gi")] = self.signal("AWADDR")
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fanout[self.signal("AWPROT", node, "gi")] = self.signal("AWPROT")
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# Write data channel
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fanout[self.signal("WVALID", node, "gi")] = wr_sel
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fanout[self.signal("WDATA", node, "gi")] = "cpuif_wr_data"
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fanout[self.signal("WSTRB", node, "gi")] = "cpuif_wr_byte_en"
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# Write response channel (master -> slave)
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fanout[self.signal("BREADY", node, "gi")] = self.signal("BREADY")
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# Read address channel
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fanout[self.signal("ARVALID", node, "gi")] = rd_sel
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fanout[self.signal("ARADDR", node, "gi")] = self.signal("ARADDR")
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fanout[self.signal("ARPROT", node, "gi")] = self.signal("ARPROT")
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# Read data channel (master -> slave)
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fanout[self.signal("RREADY", node, "gi")] = self.signal("RREADY")
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return "\n".join(f"assign {lhs} = {rhs};" for lhs, rhs in fanout.items())
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def fanin(self, node: AddressableNode | None = None) -> str:
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fanin: dict[str, str] = {}
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def signal(
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self,
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signal: str,
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node: AddressableNode | None = None,
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indexer: str | None = None,
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) -> str:
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if node is None:
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fanin["cpuif_rd_ack"] = "'0"
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fanin["cpuif_rd_err"] = "'0"
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else:
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# Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
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fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
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fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
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return f"s_axil_{signal}"
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return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
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base = f"m_axil_{node.inst_name}_{signal}"
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if not self.check_is_array(node):
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if node.current_idx is not None:
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return f"{base}_{'_'.join(map(str, node.current_idx))}"
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return base
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def readback(self, node: AddressableNode | None = None) -> str:
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fanin: dict[str, str] = {}
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if node is None:
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fanin["cpuif_rd_data"] = "'0"
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else:
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fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
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return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
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if indexer is None:
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return f"{base}[N_{node.inst_name.upper()}S]"
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return f"{base}[{indexer}]"
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