Refactor tests (better grouping + cocotb support) (#15)

* initial refactor

* fix cocotb tests

* fix typecheck

* install verilator

tests/cocotb/apb3/smoke/test_register_access.py

@@ -0,0 +1,123 @@
+"""APB3 smoke tests for generated multi-register design."""
+
+import cocotb
+from cocotb.triggers import Timer
+
+WRITE_ADDR = 0x0
+READ_ADDR = 0x8
+WRITE_DATA = 0xCAFEBABE
+READ_DATA = 0x0BAD_F00D
+
+
+class _Apb3SlaveShim:
+    def __init__(self, dut):
+        prefix = "s_apb"
+        self.PSEL = getattr(dut, f"{prefix}_PSELx")
+        self.PENABLE = getattr(dut, f"{prefix}_PENABLE")
+        self.PWRITE = getattr(dut, f"{prefix}_PWRITE")
+        self.PADDR = getattr(dut, f"{prefix}_PADDR")
+        self.PWDATA = getattr(dut, f"{prefix}_PWDATA")
+        self.PRDATA = getattr(dut, f"{prefix}_PRDATA")
+        self.PREADY = getattr(dut, f"{prefix}_PREADY")
+        self.PSLVERR = getattr(dut, f"{prefix}_PSLVERR")
+
+
+class _Apb3MasterShim:
+    def __init__(self, dut, base: str):
+        self.PSEL = getattr(dut, f"{base}_PSELx")
+        self.PENABLE = getattr(dut, f"{base}_PENABLE")
+        self.PWRITE = getattr(dut, f"{base}_PWRITE")
+        self.PADDR = getattr(dut, f"{base}_PADDR")
+        self.PWDATA = getattr(dut, f"{base}_PWDATA")
+        self.PRDATA = getattr(dut, f"{base}_PRDATA")
+        self.PREADY = getattr(dut, f"{base}_PREADY")
+        self.PSLVERR = getattr(dut, f"{base}_PSLVERR")
+
+
+def _apb3_slave(dut):
+    return getattr(dut, "s_apb", None) or _Apb3SlaveShim(dut)
+
+
+def _apb3_master(dut, base: str):
+    return getattr(dut, base, None) or _Apb3MasterShim(dut, base)
+
+
+@cocotb.test()
+async def test_apb3_read_write_paths(dut):
+    """Exercise APB3 slave interface and observe master fanout."""
+    s_apb = _apb3_slave(dut)
+    masters = {
+        "reg1": _apb3_master(dut, "m_apb_reg1"),
+        "reg2": _apb3_master(dut, "m_apb_reg2"),
+        "reg3": _apb3_master(dut, "m_apb_reg3"),
+    }
+
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    s_apb.PWRITE.value = 0
+    s_apb.PADDR.value = 0
+    s_apb.PWDATA.value = 0
+
+    for master in masters.values():
+        master.PRDATA.value = 0
+        master.PREADY.value = 0
+        master.PSLVERR.value = 0
+
+    await Timer(1, units="ns")
+
+    # Write to reg1
+    masters["reg1"].PREADY.value = 1
+    s_apb.PADDR.value = WRITE_ADDR
+    s_apb.PWDATA.value = WRITE_DATA
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+
+    await Timer(1, units="ns")
+
+    assert int(masters["reg1"].PSEL.value) == 1, "reg1 should be selected for write"
+    assert int(masters["reg1"].PWRITE.value) == 1, "Write should propagate to master"
+    assert int(masters["reg1"].PADDR.value) == WRITE_ADDR, "Address should reach selected master"
+    assert int(masters["reg1"].PWDATA.value) == WRITE_DATA, "Write data should fan out"
+
+    for name, master in masters.items():
+        if name != "reg1":
+            assert int(master.PSEL.value) == 0, f"{name} must idle during reg1 write"
+
+    assert int(s_apb.PREADY.value) == 1, "Ready must reflect selected master"
+    assert int(s_apb.PSLVERR.value) == 0, "Write should not signal error"
+
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    s_apb.PWRITE.value = 0
+    masters["reg1"].PREADY.value = 0
+    await Timer(1, units="ns")
+
+    # Read from reg3
+    masters["reg3"].PRDATA.value = READ_DATA
+    masters["reg3"].PREADY.value = 1
+    masters["reg3"].PSLVERR.value = 0
+
+    s_apb.PADDR.value = READ_ADDR
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    s_apb.PWRITE.value = 0
+
+    await Timer(1, units="ns")
+
+    assert int(masters["reg3"].PSEL.value) == 1, "reg3 should be selected for read"
+    assert int(masters["reg3"].PWRITE.value) == 0, "Read should clear write"
+    assert int(masters["reg3"].PADDR.value) == READ_ADDR, "Address should reach read target"
+
+    for name, master in masters.items():
+        if name != "reg3":
+            assert int(master.PSEL.value) == 0, f"{name} must idle during reg3 read"
+
+    assert int(s_apb.PRDATA.value) == READ_DATA, "Read data should return to slave"
+    assert int(s_apb.PREADY.value) == 1, "Read should acknowledge"
+    assert int(s_apb.PSLVERR.value) == 0, "Read should not signal error"
+
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    masters["reg3"].PREADY.value = 0
+    await Timer(1, units="ns")

tests/cocotb/apb3/smoke/test_runner.py

@@ -0,0 +1,50 @@
+"""Pytest wrapper launching the APB3 cocotb smoke test."""
+
+from pathlib import Path
+
+import pytest
+
+from peakrdl_busdecoder.cpuif.apb3.apb3_cpuif_flat import APB3CpuifFlat
+
+try:  # pragma: no cover - optional dependency shim
+    from cocotb.runner import get_runner
+except ImportError:  # pragma: no cover
+    from cocotb_tools.runner import get_runner
+
+from tests.cocotb_lib.utils import compile_rdl_and_export, get_verilog_sources
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+def test_apb3_smoke(tmp_path: Path) -> None:
+    """Compile the APB3 design and execute the cocotb smoke test."""
+    repo_root = Path(__file__).resolve().parents[4]
+
+    module_path, package_path = compile_rdl_and_export(
+        str(repo_root / "tests" / "cocotb_lib" / "multiple_reg.rdl"),
+        "multi_reg",
+        tmp_path,
+        cpuif_cls=APB3CpuifFlat,
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "apb3_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    build_dir = tmp_path / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=build_dir,
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.apb3.smoke.test_register_access",
+        build_dir=build_dir,
+        log_file=str(tmp_path / "sim.log"),
+    )