Refactor tests (better grouping + cocotb support) (#15)
* initial refactor * fix cocotb tests * fix typecheck * install verilator
This commit is contained in:
Arnav Sacheti
@@ -1 +0,0 @@
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"""Unit test package for PeakRDL BusDecoder."""
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@@ -5,52 +5,71 @@
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from pathlib import Path
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from tempfile import NamedTemporaryFile
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from typing import Iterable, Mapping, Optional
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from collections.abc import Callable
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import pytest
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from systemrdl import RDLCompileError, RDLCompiler
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from systemrdl.node import AddrmapNode
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@pytest.fixture
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def compile_rdl(tmp_path: Path):
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"""Compile inline SystemRDL source and return the elaborated root node.
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def external_nested_rdl(compile_rdl: Callable[..., AddrmapNode]) -> AddrmapNode:
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"""Create an RDL design with external nested addressable components.
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Parameters
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----------
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tmp_path:
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Temporary directory provided by pytest.
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This tests the scenario where an addrmap contains external children
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that themselves have external addressable children.
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The decoder should only generate select signals for the top-level
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external children, not their internal structure.
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"""
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rdl_source = """
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mem queue_t {
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name = "Queue";
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mementries = 1024;
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memwidth = 64;
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};
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def _compile(
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source: str,
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*,
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top: Optional[str] = None,
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defines: Optional[Mapping[str, object]] = None,
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include_paths: Optional[Iterable[Path | str]] = None,
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):
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compiler = RDLCompiler()
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addrmap port_t {
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name = "Port";
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desc = "";
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for key, value in (defines or {}).items():
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compiler.define(key, value)
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external queue_t common[3] @ 0x0 += 0x2000;
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external queue_t response @ 0x6000;
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};
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for include_path in include_paths or ():
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compiler.add_include_path(str(include_path))
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addrmap buffer_t {
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name = "Buffer";
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desc = "";
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# Use delete=False to keep the file around after closing
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with NamedTemporaryFile("w", suffix=".rdl", dir=tmp_path, delete=False) as tmp_file:
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tmp_file.write(source)
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tmp_file.flush()
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port_t multicast @ 0x0;
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port_t port [16] @ 0x8000 += 0x8000;
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};
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"""
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return compile_rdl(rdl_source, top="buffer_t")
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try:
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compiler.compile_file(tmp_file.name)
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if top is not None:
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root = compiler.elaborate(top)
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return root.top
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root = compiler.elaborate()
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return root.top
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except RDLCompileError:
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# Print error messages if available
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if hasattr(compiler, "print_messages"):
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compiler.print_messages()
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raise
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return _compile
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@pytest.fixture
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def nested_addrmap_rdl(compile_rdl: Callable[..., AddrmapNode]) -> AddrmapNode:
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"""Create an RDL design with nested non-external addrmaps for testing depth control."""
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rdl_source = """
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addrmap level2 {
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reg {
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field { sw=rw; hw=r; } data2[31:0];
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} reg2 @ 0x0;
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reg {
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field { sw=rw; hw=r; } data2b[31:0];
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} reg2b @ 0x4;
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};
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addrmap level1 {
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reg {
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field { sw=rw; hw=r; } data1[31:0];
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} reg1 @ 0x0;
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level2 inner2 @ 0x10;
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};
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addrmap level0 {
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level1 inner1 @ 0x0;
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};
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"""
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return compile_rdl(rdl_source, top="level0")
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@@ -1,285 +0,0 @@
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"""Tests for body classes used in code generation."""
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import pytest
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from peakrdl_busdecoder.body import (
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Body,
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CombinationalBody,
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ForLoopBody,
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IfBody,
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StructBody,
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)
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class TestBody:
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"""Test the base Body class."""
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def test_empty_body(self):
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"""Test empty body returns empty string."""
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body = Body()
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assert str(body) == ""
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assert not body # Should be falsy when empty
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def test_add_single_line(self):
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"""Test adding a single line to body."""
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body = Body()
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body += "line1"
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assert str(body) == "line1"
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assert body # Should be truthy when not empty
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def test_add_multiple_lines(self):
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"""Test adding multiple lines to body."""
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body = Body()
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body += "line1"
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body += "line2"
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body += "line3"
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expected = "line1\nline2\nline3"
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assert str(body) == expected
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def test_add_returns_self(self):
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"""Test that add operation returns self for chaining."""
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body = Body()
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body += "line1"
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body += "line2"
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# Chaining works because += returns self
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assert len(body.lines) == 2
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def test_add_nested_body(self):
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"""Test adding another body as a line."""
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outer = Body()
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inner = Body()
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inner += "inner1"
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inner += "inner2"
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outer += "outer1"
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outer += inner
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outer += "outer2"
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expected = "outer1\ninner1\ninner2\nouter2"
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assert str(outer) == expected
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class TestForLoopBody:
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"""Test the ForLoopBody class."""
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def test_genvar_for_loop(self):
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"""Test genvar-style for loop."""
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body = ForLoopBody("genvar", "i", 4)
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body += "statement1;"
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body += "statement2;"
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result = str(body)
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assert "for (genvar i = 0; i < 4; i++)" in result
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assert "statement1;" in result
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assert "statement2;" in result
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assert "end" in result
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def test_int_for_loop(self):
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"""Test int-style for loop."""
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body = ForLoopBody("int", "j", 8)
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body += "assignment = value;"
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result = str(body)
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assert "for (int j = 0; j < 8; j++)" in result
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assert "assignment = value;" in result
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assert "end" in result
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def test_empty_for_loop(self):
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"""Test empty for loop."""
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body = ForLoopBody("genvar", "k", 2)
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result = str(body)
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# Empty for loop should still have structure
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assert "for (genvar k = 0; k < 2; k++)" in result
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def test_nested_for_loops(self):
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"""Test nested for loops."""
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outer = ForLoopBody("genvar", "i", 3)
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inner = ForLoopBody("genvar", "j", 2)
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inner += "nested_statement;"
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outer += inner
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result = str(outer)
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assert "for (genvar i = 0; i < 3; i++)" in result
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assert "for (genvar j = 0; j < 2; j++)" in result
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assert "nested_statement;" in result
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class TestIfBody:
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"""Test the IfBody class."""
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def test_simple_if(self):
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"""Test simple if statement."""
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body = IfBody()
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with body.cm("condition1") as b:
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b += "statement1;"
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result = str(body)
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assert "if (condition1)" in result
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assert "statement1;" in result
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assert "end" in result
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def test_if_else(self):
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"""Test if-else statement."""
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body = IfBody()
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with body.cm("condition1") as b:
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b += "if_statement;"
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with body.cm(None) as b: # None for else
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b += "else_statement;"
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result = str(body)
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assert "if (condition1)" in result
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assert "if_statement;" in result
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assert "else" in result
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assert "else_statement;" in result
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def test_if_elif_else(self):
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"""Test if-elif-else chain."""
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body = IfBody()
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with body.cm("condition1") as b:
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b += "statement1;"
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with body.cm("condition2") as b:
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b += "statement2;"
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with body.cm(None) as b: # None for else
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b += "statement3;"
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result = str(body)
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assert "if (condition1)" in result
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assert "statement1;" in result
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assert "else if (condition2)" in result
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assert "statement2;" in result
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assert "else" in result
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assert "statement3;" in result
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def test_multiple_elif(self):
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"""Test multiple elif statements."""
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body = IfBody()
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with body.cm("cond1") as b:
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b += "stmt1;"
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with body.cm("cond2") as b:
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b += "stmt2;"
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with body.cm("cond3") as b:
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b += "stmt3;"
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result = str(body)
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assert "if (cond1)" in result
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assert "else if (cond2)" in result
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assert "else if (cond3)" in result
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def test_empty_if_branches(self):
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"""Test if statement with empty branches."""
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body = IfBody()
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with body.cm("condition"):
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pass
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result = str(body)
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assert "if (condition)" in result
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def test_nested_if(self):
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"""Test nested if statements."""
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outer = IfBody()
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with outer.cm("outer_cond") as outer_body:
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inner = IfBody()
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with inner.cm("inner_cond") as inner_body:
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inner_body += "nested_statement;"
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outer_body += inner
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result = str(outer)
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assert "if (outer_cond)" in result
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assert "if (inner_cond)" in result
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assert "nested_statement;" in result
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class TestCombinationalBody:
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"""Test the CombinationalBody class."""
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def test_simple_combinational_block(self):
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"""Test simple combinational block."""
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body = CombinationalBody()
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body += "assign1 = value1;"
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body += "assign2 = value2;"
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result = str(body)
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assert "always_comb" in result
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assert "begin" in result
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assert "assign1 = value1;" in result
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assert "assign2 = value2;" in result
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assert "end" in result
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def test_empty_combinational_block(self):
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"""Test empty combinational block."""
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body = CombinationalBody()
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result = str(body)
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assert "always_comb" in result
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assert "begin" in result
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assert "end" in result
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def test_combinational_with_if_statement(self):
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"""Test combinational block with if statement."""
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cb = CombinationalBody()
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ifb = IfBody()
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with ifb.cm("condition") as b:
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b += "assignment = value;"
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cb += ifb
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result = str(cb)
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assert "always_comb" in result
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assert "if (condition)" in result
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assert "assignment = value;" in result
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class TestStructBody:
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"""Test the StructBody class."""
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def test_simple_struct(self):
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"""Test simple struct definition."""
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body = StructBody("my_struct_t", packed=True, typedef=True)
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body += "logic [7:0] field1;"
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body += "logic field2;"
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result = str(body)
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assert "typedef struct packed" in result
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assert "my_struct_t" in result
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assert "logic [7:0] field1;" in result
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assert "logic field2;" in result
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def test_unpacked_struct(self):
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"""Test unpacked struct definition."""
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body = StructBody("unpacked_t", packed=False, typedef=True)
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body += "int field1;"
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result = str(body)
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assert "typedef struct" in result
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assert "packed" not in result or "typedef struct {" in result
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assert "unpacked_t" in result
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def test_struct_without_typedef(self):
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"""Test struct without typedef."""
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body = StructBody("my_struct", packed=True, typedef=False)
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body += "logic field;"
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result = str(body)
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# When typedef=False, packed is not used
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assert "struct {" in result
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assert "typedef" not in result
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assert "my_struct" in result
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def test_empty_struct(self):
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"""Test empty struct."""
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body = StructBody("empty_t", packed=True, typedef=True)
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result = str(body)
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assert "typedef struct packed" in result
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assert "empty_t" in result
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def test_nested_struct(self):
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"""Test struct with nested struct."""
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outer = StructBody("outer_t", packed=True, typedef=True)
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inner = StructBody("inner_t", packed=True, typedef=True)
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inner += "logic field1;"
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outer += "logic field2;"
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outer += str(inner) # Include inner struct as a string
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result = str(outer)
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assert "outer_t" in result
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assert "field2;" in result
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# Inner struct should appear in the string
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assert "inner_t" in result
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@@ -1,329 +0,0 @@
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"""Integration tests for the BusDecoderExporter."""
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import os
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from pathlib import Path
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import pytest
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from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
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from peakrdl_busdecoder.exporter import BusDecoderExporter
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class TestBusDecoderExporter:
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"""Test the top-level BusDecoderExporter."""
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def test_simple_register_export(self, compile_rdl, tmp_path):
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"""Test exporting a simple register."""
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rdl_source = """
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addrmap simple_reg {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="simple_reg")
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exporter = BusDecoderExporter()
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output_dir = str(tmp_path)
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exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
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# Check that output files are created
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module_file = tmp_path / "simple_reg.sv"
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package_file = tmp_path / "simple_reg_pkg.sv"
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assert module_file.exists()
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assert package_file.exists()
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# Check basic content
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module_content = module_file.read_text()
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assert "module simple_reg" in module_content
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assert "my_reg" in module_content
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package_content = package_file.read_text()
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assert "package simple_reg_pkg" in package_content
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def test_register_array_export(self, compile_rdl, tmp_path):
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"""Test exporting a register array."""
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rdl_source = """
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addrmap reg_array {
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reg {
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field {
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sw=rw;
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hw=r;
|
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} data[31:0];
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} my_regs[4] @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="reg_array")
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exporter = BusDecoderExporter()
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output_dir = str(tmp_path)
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exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
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# Check that output files are created
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module_file = tmp_path / "reg_array.sv"
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assert module_file.exists()
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module_content = module_file.read_text()
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assert "module reg_array" in module_content
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assert "my_regs" in module_content
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def test_nested_addrmap_export(self, compile_rdl, tmp_path):
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"""Test exporting nested addrmaps."""
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rdl_source = """
|
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addrmap inner_block {
|
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reg {
|
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field {
|
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sw=rw;
|
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hw=r;
|
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} data[31:0];
|
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} inner_reg @ 0x0;
|
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};
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|
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addrmap outer_block {
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inner_block inner @ 0x0;
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};
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"""
|
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top = compile_rdl(rdl_source, top="outer_block")
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|
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exporter = BusDecoderExporter()
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output_dir = str(tmp_path)
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exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
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# Check that output files are created
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module_file = tmp_path / "outer_block.sv"
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assert module_file.exists()
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|
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module_content = module_file.read_text()
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assert "module outer_block" in module_content
|
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assert "inner" in module_content
|
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assert "inner_reg" in module_content
|
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|
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def test_custom_module_name(self, compile_rdl, tmp_path):
|
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"""Test exporting with custom module name."""
|
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rdl_source = """
|
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addrmap my_addrmap {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
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} my_reg @ 0x0;
|
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};
|
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"""
|
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top = compile_rdl(rdl_source, top="my_addrmap")
|
||||
|
||||
exporter = BusDecoderExporter()
|
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output_dir = str(tmp_path)
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exporter.export(top, output_dir, module_name="custom_module", cpuif_cls=APB4Cpuif)
|
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|
||||
# Check that output files use custom name
|
||||
module_file = tmp_path / "custom_module.sv"
|
||||
package_file = tmp_path / "custom_module_pkg.sv"
|
||||
|
||||
assert module_file.exists()
|
||||
assert package_file.exists()
|
||||
|
||||
module_content = module_file.read_text()
|
||||
assert "module custom_module" in module_content
|
||||
|
||||
def test_custom_package_name(self, compile_rdl, tmp_path):
|
||||
"""Test exporting with custom package name."""
|
||||
rdl_source = """
|
||||
addrmap my_addrmap {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="my_addrmap")
|
||||
|
||||
exporter = BusDecoderExporter()
|
||||
output_dir = str(tmp_path)
|
||||
exporter.export(top, output_dir, package_name="custom_pkg", cpuif_cls=APB4Cpuif)
|
||||
|
||||
# Check that output files use custom package name
|
||||
package_file = tmp_path / "custom_pkg.sv"
|
||||
assert package_file.exists()
|
||||
|
||||
package_content = package_file.read_text()
|
||||
assert "package custom_pkg" in package_content
|
||||
|
||||
def test_multiple_registers(self, compile_rdl, tmp_path):
|
||||
"""Test exporting multiple registers."""
|
||||
rdl_source = """
|
||||
addrmap multi_reg {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} reg1 @ 0x0;
|
||||
|
||||
reg {
|
||||
field {
|
||||
sw=r;
|
||||
hw=w;
|
||||
} status[15:0];
|
||||
} reg2 @ 0x4;
|
||||
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} control[7:0];
|
||||
} reg3 @ 0x8;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="multi_reg")
|
||||
|
||||
exporter = BusDecoderExporter()
|
||||
output_dir = str(tmp_path)
|
||||
exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
|
||||
|
||||
module_file = tmp_path / "multi_reg.sv"
|
||||
assert module_file.exists()
|
||||
|
||||
module_content = module_file.read_text()
|
||||
assert "module multi_reg" in module_content
|
||||
assert "reg1" in module_content
|
||||
assert "reg2" in module_content
|
||||
assert "reg3" in module_content
|
||||
|
||||
|
||||
class TestAPB4Interface:
|
||||
"""Test APB4 CPU interface generation."""
|
||||
|
||||
def test_apb4_port_declaration(self, compile_rdl, tmp_path):
|
||||
"""Test that APB4 interface ports are generated."""
|
||||
rdl_source = """
|
||||
addrmap apb_test {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="apb_test")
|
||||
|
||||
exporter = BusDecoderExporter()
|
||||
output_dir = str(tmp_path)
|
||||
exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
|
||||
|
||||
module_file = tmp_path / "apb_test.sv"
|
||||
module_content = module_file.read_text()
|
||||
|
||||
# Check for APB4 signals
|
||||
assert "PSEL" in module_content or "psel" in module_content
|
||||
assert "PENABLE" in module_content or "penable" in module_content
|
||||
assert "PWRITE" in module_content or "pwrite" in module_content
|
||||
assert "PADDR" in module_content or "paddr" in module_content
|
||||
assert "PWDATA" in module_content or "pwdata" in module_content
|
||||
assert "PRDATA" in module_content or "prdata" in module_content
|
||||
assert "PREADY" in module_content or "pready" in module_content
|
||||
|
||||
def test_apb4_read_write_logic(self, compile_rdl, tmp_path):
|
||||
"""Test that APB4 read/write logic is generated."""
|
||||
rdl_source = """
|
||||
addrmap apb_rw {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="apb_rw")
|
||||
|
||||
exporter = BusDecoderExporter()
|
||||
output_dir = str(tmp_path)
|
||||
exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
|
||||
|
||||
module_file = tmp_path / "apb_rw.sv"
|
||||
module_content = module_file.read_text()
|
||||
|
||||
# Basic sanity checks for logic generation
|
||||
assert "always" in module_content or "assign" in module_content
|
||||
assert "my_reg" in module_content
|
||||
|
||||
def test_nested_addrmap_with_array_stride(self, compile_rdl, tmp_path):
|
||||
"""Test that nested addrmaps with arrays use correct stride values."""
|
||||
rdl_source = """
|
||||
addrmap inner_block {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} inner_reg @ 0x0;
|
||||
};
|
||||
|
||||
addrmap outer_block {
|
||||
inner_block inner[4] @ 0x0 += 0x100;
|
||||
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} outer_data[31:0];
|
||||
} outer_reg @ 0x400;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="outer_block")
|
||||
|
||||
exporter = BusDecoderExporter()
|
||||
output_dir = str(tmp_path)
|
||||
exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
|
||||
|
||||
module_file = tmp_path / "outer_block.sv"
|
||||
module_content = module_file.read_text()
|
||||
|
||||
# Check that the generated code uses the correct stride (0x100 = 256)
|
||||
# not the array dimension (4)
|
||||
# The decode logic should contain something like: i0)*11'h100 or i0)*256
|
||||
assert "i0)*11'h100" in module_content or "i0)*'h100" in module_content, \
|
||||
"Array stride should be 0x100 (256), not the dimension value (4)"
|
||||
|
||||
# Ensure it's NOT using the incorrect dimension value
|
||||
assert (
|
||||
"i0)*11'h4" not in module_content
|
||||
and "i0)*4" not in module_content
|
||||
), "Should not use array dimension (4) as stride"
|
||||
|
||||
def test_multidimensional_array_strides(self, compile_rdl, tmp_path):
|
||||
"""Test that multidimensional arrays calculate correct strides for each dimension."""
|
||||
rdl_source = """
|
||||
addrmap test_block {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg[2][3] @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test_block")
|
||||
|
||||
exporter = BusDecoderExporter()
|
||||
output_dir = str(tmp_path)
|
||||
exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
|
||||
|
||||
module_file = tmp_path / "test_block.sv"
|
||||
module_content = module_file.read_text()
|
||||
# For a [2][3] array where each register is 4 bytes:
|
||||
# i0 (leftmost/slowest) should have stride = 3 * 4 = 12 (0xc)
|
||||
# i1 (rightmost/fastest) should have stride = 4 (0x4)
|
||||
assert ("i0)*5'hc" in module_content or "i0)*12" in module_content), \
|
||||
"i0 should use stride 12 (0xc) for [2][3] array"
|
||||
assert ("i1)*5'h4" in module_content or "i1)*4" in module_content), \
|
||||
"i1 should use stride 4 for [2][3] array"
|
||||
@@ -1,79 +1,16 @@
|
||||
"""Test handling of external nested addressable components."""
|
||||
|
||||
from collections.abc import Callable
|
||||
from pathlib import Path
|
||||
from tempfile import TemporaryDirectory
|
||||
|
||||
import pytest
|
||||
from systemrdl.node import AddrmapNode
|
||||
|
||||
from peakrdl_busdecoder import BusDecoderExporter
|
||||
from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
|
||||
|
||||
|
||||
@pytest.fixture
|
||||
def external_nested_rdl(compile_rdl):
|
||||
"""Create an RDL design with external nested addressable components.
|
||||
|
||||
This tests the scenario where an addrmap contains external children
|
||||
that themselves have external addressable children.
|
||||
The decoder should only generate select signals for the top-level
|
||||
external children, not their internal structure.
|
||||
"""
|
||||
rdl_source = """
|
||||
mem queue_t {
|
||||
name = "Queue";
|
||||
mementries = 1024;
|
||||
memwidth = 64;
|
||||
};
|
||||
|
||||
addrmap port_t {
|
||||
name = "Port";
|
||||
desc = "";
|
||||
|
||||
external queue_t common[3] @ 0x0 += 0x2000;
|
||||
external queue_t response @ 0x6000;
|
||||
};
|
||||
|
||||
addrmap buffer_t {
|
||||
name = "Buffer";
|
||||
desc = "";
|
||||
|
||||
port_t multicast @ 0x0;
|
||||
port_t port [16] @ 0x8000 += 0x8000;
|
||||
};
|
||||
"""
|
||||
return compile_rdl(rdl_source, top="buffer_t")
|
||||
|
||||
|
||||
@pytest.fixture
|
||||
def nested_addrmap_rdl(compile_rdl):
|
||||
"""Create an RDL design with nested non-external addrmaps for testing depth control."""
|
||||
rdl_source = """
|
||||
addrmap level2 {
|
||||
reg {
|
||||
field { sw=rw; hw=r; } data2[31:0];
|
||||
} reg2 @ 0x0;
|
||||
|
||||
reg {
|
||||
field { sw=rw; hw=r; } data2b[31:0];
|
||||
} reg2b @ 0x4;
|
||||
};
|
||||
|
||||
addrmap level1 {
|
||||
reg {
|
||||
field { sw=rw; hw=r; } data1[31:0];
|
||||
} reg1 @ 0x0;
|
||||
|
||||
level2 inner2 @ 0x10;
|
||||
};
|
||||
|
||||
addrmap level0 {
|
||||
level1 inner1 @ 0x0;
|
||||
};
|
||||
"""
|
||||
return compile_rdl(rdl_source, top="level0")
|
||||
|
||||
|
||||
def test_external_nested_components_generate_correct_decoder(external_nested_rdl):
|
||||
def test_external_nested_components_generate_correct_decoder(external_nested_rdl: AddrmapNode) -> None:
|
||||
"""Test that external nested components generate correct decoder logic.
|
||||
|
||||
The decoder should:
|
||||
@@ -109,7 +46,7 @@ def test_external_nested_components_generate_correct_decoder(external_nested_rdl
|
||||
assert "logic [15:0]port;" in content
|
||||
|
||||
|
||||
def test_external_nested_components_generate_correct_interfaces(external_nested_rdl):
|
||||
def test_external_nested_components_generate_correct_interfaces(external_nested_rdl: AddrmapNode) -> None:
|
||||
"""Test that external nested components generate correct interface ports.
|
||||
|
||||
The module should have:
|
||||
@@ -140,7 +77,7 @@ def test_external_nested_components_generate_correct_interfaces(external_nested_
|
||||
assert "m_apb_response" not in content
|
||||
|
||||
|
||||
def test_non_external_nested_components_are_descended(compile_rdl):
|
||||
def test_non_external_nested_components_are_descended(compile_rdl: Callable[..., AddrmapNode]) -> None:
|
||||
"""Test that non-external nested components are still descended into.
|
||||
|
||||
This is a regression test to ensure we didn't break normal nested
|
||||
@@ -175,7 +112,7 @@ def test_non_external_nested_components_are_descended(compile_rdl):
|
||||
assert "inner_reg" in content
|
||||
|
||||
|
||||
def test_max_decode_depth_parameter_exists(compile_rdl):
|
||||
def test_max_decode_depth_parameter_exists(compile_rdl: Callable[..., AddrmapNode]) -> None:
|
||||
"""Test that max_decode_depth parameter can be set."""
|
||||
rdl_source = """
|
||||
addrmap simple {
|
||||
|
||||
@@ -1,312 +0,0 @@
|
||||
"""Tests for code generation classes."""
|
||||
|
||||
|
||||
|
||||
import pytest
|
||||
|
||||
from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
|
||||
from peakrdl_busdecoder.decode_logic_gen import DecodeLogicFlavor, DecodeLogicGenerator
|
||||
from peakrdl_busdecoder.design_state import DesignState
|
||||
from peakrdl_busdecoder.exporter import BusDecoderExporter
|
||||
from peakrdl_busdecoder.struct_gen import StructGenerator
|
||||
|
||||
|
||||
class TestDecodeLogicGenerator:
|
||||
"""Test the DecodeLogicGenerator."""
|
||||
|
||||
def test_decode_logic_read(self, compile_rdl):
|
||||
"""Test decode logic generation for read operations."""
|
||||
rdl_source = """
|
||||
addrmap test {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test")
|
||||
|
||||
ds = DesignState(top, {})
|
||||
gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.READ)
|
||||
|
||||
# Basic sanity check - it should initialize
|
||||
assert gen is not None
|
||||
assert gen._flavor == DecodeLogicFlavor.READ
|
||||
|
||||
def test_decode_logic_write(self, compile_rdl):
|
||||
"""Test decode logic generation for write operations."""
|
||||
rdl_source = """
|
||||
addrmap test {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test")
|
||||
|
||||
ds = DesignState(top, {})
|
||||
gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.WRITE)
|
||||
|
||||
assert gen is not None
|
||||
assert gen._flavor == DecodeLogicFlavor.WRITE
|
||||
|
||||
def test_cpuif_addr_predicate(self, compile_rdl):
|
||||
"""Test address predicate generation."""
|
||||
rdl_source = """
|
||||
addrmap test {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x100;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test")
|
||||
|
||||
ds = DesignState(top, {})
|
||||
gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.READ)
|
||||
|
||||
# Get the register node
|
||||
reg_node = None
|
||||
for child in top.children():
|
||||
if child.inst_name == "my_reg":
|
||||
reg_node = child
|
||||
break
|
||||
assert reg_node is not None
|
||||
|
||||
predicates = gen.cpuif_addr_predicate(reg_node)
|
||||
|
||||
# Should return a list of conditions
|
||||
assert isinstance(predicates, list)
|
||||
assert len(predicates) > 0
|
||||
# Should check address bounds
|
||||
for pred in predicates:
|
||||
assert "cpuif_rd_addr" in pred or ">=" in pred or "<" in pred
|
||||
|
||||
def test_decode_logic_flavor_enum(self):
|
||||
"""Test DecodeLogicFlavor enum values."""
|
||||
assert DecodeLogicFlavor.READ.value == "rd"
|
||||
assert DecodeLogicFlavor.WRITE.value == "wr"
|
||||
|
||||
assert DecodeLogicFlavor.READ.cpuif_address == "cpuif_rd_addr"
|
||||
assert DecodeLogicFlavor.WRITE.cpuif_address == "cpuif_wr_addr"
|
||||
|
||||
assert DecodeLogicFlavor.READ.cpuif_select == "cpuif_rd_sel"
|
||||
assert DecodeLogicFlavor.WRITE.cpuif_select == "cpuif_wr_sel"
|
||||
|
||||
|
||||
class TestStructGenerator:
|
||||
"""Test the StructGenerator."""
|
||||
|
||||
def test_simple_struct_generation(self, compile_rdl):
|
||||
"""Test struct generation for simple register."""
|
||||
rdl_source = """
|
||||
addrmap test {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test")
|
||||
|
||||
ds = DesignState(top, {})
|
||||
gen = StructGenerator(ds)
|
||||
|
||||
# Should generate struct definition
|
||||
assert gen is not None
|
||||
result = str(gen)
|
||||
|
||||
# Should contain struct declaration
|
||||
assert "struct" in result or "typedef" in result
|
||||
|
||||
def test_nested_struct_generation(self, compile_rdl):
|
||||
"""Test struct generation for nested addrmaps."""
|
||||
rdl_source = """
|
||||
addrmap inner {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} inner_reg @ 0x0;
|
||||
};
|
||||
|
||||
addrmap outer {
|
||||
inner my_inner @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="outer")
|
||||
|
||||
ds = DesignState(top, {})
|
||||
gen = StructGenerator(ds)
|
||||
|
||||
# Walk the tree to generate structs
|
||||
from systemrdl.walker import RDLWalker
|
||||
|
||||
walker = RDLWalker()
|
||||
walker.walk(top, gen, skip_top=True)
|
||||
|
||||
result = str(gen)
|
||||
|
||||
# Should contain struct declaration
|
||||
assert "struct" in result or "typedef" in result
|
||||
# The struct should reference the inner component
|
||||
assert "my_inner" in result
|
||||
|
||||
def test_array_struct_generation(self, compile_rdl):
|
||||
"""Test struct generation for register arrays."""
|
||||
rdl_source = """
|
||||
addrmap test {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_regs[4] @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test")
|
||||
|
||||
ds = DesignState(top, {})
|
||||
gen = StructGenerator(ds)
|
||||
|
||||
# Walk the tree to generate structs
|
||||
from systemrdl.walker import RDLWalker
|
||||
|
||||
walker = RDLWalker()
|
||||
walker.walk(top, gen, skip_top=True)
|
||||
|
||||
result = str(gen)
|
||||
|
||||
# Should contain array notation
|
||||
assert "[" in result and "]" in result
|
||||
# Should reference the register
|
||||
assert "my_regs" in result
|
||||
|
||||
|
||||
class TestDesignState:
|
||||
"""Test the DesignState class."""
|
||||
|
||||
def test_design_state_basic(self, compile_rdl):
|
||||
"""Test basic DesignState initialization."""
|
||||
rdl_source = """
|
||||
addrmap test {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test")
|
||||
|
||||
ds = DesignState(top, {})
|
||||
|
||||
assert ds.top_node == top
|
||||
assert ds.module_name == "test"
|
||||
assert ds.package_name == "test_pkg"
|
||||
assert ds.cpuif_data_width == 32 # Should infer from 32-bit field
|
||||
assert ds.addr_width > 0
|
||||
|
||||
def test_design_state_custom_module_name(self, compile_rdl):
|
||||
"""Test DesignState with custom module name."""
|
||||
rdl_source = """
|
||||
addrmap test {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test")
|
||||
|
||||
ds = DesignState(top, {"module_name": "custom_module"})
|
||||
|
||||
assert ds.module_name == "custom_module"
|
||||
assert ds.package_name == "custom_module_pkg"
|
||||
|
||||
def test_design_state_custom_package_name(self, compile_rdl):
|
||||
"""Test DesignState with custom package name."""
|
||||
rdl_source = """
|
||||
addrmap test {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test")
|
||||
|
||||
ds = DesignState(top, {"package_name": "custom_pkg"})
|
||||
|
||||
assert ds.package_name == "custom_pkg"
|
||||
|
||||
def test_design_state_custom_address_width(self, compile_rdl):
|
||||
"""Test DesignState with custom address width."""
|
||||
rdl_source = """
|
||||
addrmap test {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test")
|
||||
|
||||
ds = DesignState(top, {"address_width": 16})
|
||||
|
||||
assert ds.addr_width == 16
|
||||
|
||||
def test_design_state_unroll_arrays(self, compile_rdl):
|
||||
"""Test DesignState with cpuif_unroll option."""
|
||||
rdl_source = """
|
||||
addrmap test {
|
||||
reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_regs[4] @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test")
|
||||
|
||||
ds = DesignState(top, {"cpuif_unroll": True})
|
||||
|
||||
assert ds.cpuif_unroll is True
|
||||
|
||||
def test_design_state_64bit_registers(self, compile_rdl):
|
||||
"""Test DesignState with wider data width."""
|
||||
rdl_source = """
|
||||
addrmap test {
|
||||
reg {
|
||||
regwidth = 32;
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
} my_reg @ 0x0;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="test")
|
||||
|
||||
ds = DesignState(top, {})
|
||||
|
||||
# Should infer 32-bit data width from field
|
||||
assert ds.cpuif_data_width == 32
|
||||
@@ -1,163 +0,0 @@
|
||||
"""Test the --unroll CLI argument functionality."""
|
||||
|
||||
from pathlib import Path
|
||||
from tempfile import TemporaryDirectory
|
||||
|
||||
import pytest
|
||||
|
||||
from peakrdl_busdecoder import BusDecoderExporter
|
||||
from peakrdl_busdecoder.cpuif.apb3 import APB3Cpuif
|
||||
from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
|
||||
|
||||
|
||||
@pytest.fixture
|
||||
def sample_rdl(compile_rdl):
|
||||
"""Create a simple RDL design with an array."""
|
||||
rdl_source = """
|
||||
addrmap top {
|
||||
reg my_reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
};
|
||||
|
||||
my_reg regs[4] @ 0x0 += 0x4;
|
||||
};
|
||||
"""
|
||||
return compile_rdl(rdl_source)
|
||||
|
||||
|
||||
def test_unroll_disabled_creates_array_interface(sample_rdl):
|
||||
"""Test that with unroll=False, array nodes are kept as arrays."""
|
||||
with TemporaryDirectory() as tmpdir:
|
||||
exporter = BusDecoderExporter()
|
||||
exporter.export(
|
||||
sample_rdl,
|
||||
tmpdir,
|
||||
cpuif_cls=APB4Cpuif,
|
||||
cpuif_unroll=False,
|
||||
)
|
||||
|
||||
# Read the generated module
|
||||
module_file = Path(tmpdir) / "top.sv"
|
||||
content = module_file.read_text()
|
||||
|
||||
# Should have a single array interface with [4] dimension
|
||||
assert "m_apb_regs [4]" in content
|
||||
|
||||
# Should have a parameter for array size
|
||||
assert "N_REGSS = 4" in content
|
||||
|
||||
# Should NOT have individual indexed interfaces
|
||||
assert "m_apb_regs_0" not in content
|
||||
assert "m_apb_regs_1" not in content
|
||||
assert "m_apb_regs_2" not in content
|
||||
assert "m_apb_regs_3" not in content
|
||||
|
||||
|
||||
def test_unroll_enabled_creates_individual_interfaces(sample_rdl):
|
||||
"""Test that with unroll=True, array elements are unrolled into separate instances."""
|
||||
with TemporaryDirectory() as tmpdir:
|
||||
exporter = BusDecoderExporter()
|
||||
exporter.export(
|
||||
sample_rdl,
|
||||
tmpdir,
|
||||
cpuif_cls=APB4Cpuif,
|
||||
cpuif_unroll=True,
|
||||
)
|
||||
|
||||
# Read the generated module
|
||||
module_file = Path(tmpdir) / "top.sv"
|
||||
content = module_file.read_text()
|
||||
|
||||
# Should have individual interfaces without array dimensions
|
||||
assert "m_apb_regs_0," in content or "m_apb_regs_0\n" in content
|
||||
assert "m_apb_regs_1," in content or "m_apb_regs_1\n" in content
|
||||
assert "m_apb_regs_2," in content or "m_apb_regs_2\n" in content
|
||||
assert "m_apb_regs_3" in content
|
||||
|
||||
# Should NOT have array interface
|
||||
assert "m_apb_regs [4]" not in content
|
||||
|
||||
# Should NOT have individual interfaces with array dimensions (the bug we're fixing)
|
||||
assert "m_apb_regs_0 [4]" not in content
|
||||
assert "m_apb_regs_1 [4]" not in content
|
||||
assert "m_apb_regs_2 [4]" not in content
|
||||
assert "m_apb_regs_3 [4]" not in content
|
||||
|
||||
# Should NOT have array size parameter when unrolled
|
||||
assert "N_REGSS" not in content
|
||||
|
||||
|
||||
def test_unroll_with_apb3(sample_rdl):
|
||||
"""Test that unroll works correctly with APB3 interface."""
|
||||
with TemporaryDirectory() as tmpdir:
|
||||
exporter = BusDecoderExporter()
|
||||
exporter.export(
|
||||
sample_rdl,
|
||||
tmpdir,
|
||||
cpuif_cls=APB3Cpuif,
|
||||
cpuif_unroll=True,
|
||||
)
|
||||
|
||||
# Read the generated module
|
||||
module_file = Path(tmpdir) / "top.sv"
|
||||
content = module_file.read_text()
|
||||
|
||||
# Should have individual APB3 interfaces
|
||||
assert "m_apb_regs_0," in content or "m_apb_regs_0\n" in content
|
||||
assert "m_apb_regs_1," in content or "m_apb_regs_1\n" in content
|
||||
assert "m_apb_regs_2," in content or "m_apb_regs_2\n" in content
|
||||
assert "m_apb_regs_3" in content
|
||||
|
||||
# Should NOT have array dimensions on unrolled interfaces
|
||||
assert "m_apb_regs_0 [4]" not in content
|
||||
|
||||
|
||||
@pytest.fixture
|
||||
def multidim_array_rdl(compile_rdl):
|
||||
"""Create an RDL design with a multi-dimensional array."""
|
||||
rdl_source = """
|
||||
addrmap top {
|
||||
reg my_reg {
|
||||
field {
|
||||
sw=rw;
|
||||
hw=r;
|
||||
} data[31:0];
|
||||
};
|
||||
|
||||
my_reg matrix[2][3] @ 0x0 += 0x4;
|
||||
};
|
||||
"""
|
||||
return compile_rdl(rdl_source)
|
||||
|
||||
|
||||
def test_unroll_multidimensional_array(multidim_array_rdl):
|
||||
"""Test that unroll works correctly with multi-dimensional arrays."""
|
||||
with TemporaryDirectory() as tmpdir:
|
||||
exporter = BusDecoderExporter()
|
||||
exporter.export(
|
||||
multidim_array_rdl,
|
||||
tmpdir,
|
||||
cpuif_cls=APB4Cpuif,
|
||||
cpuif_unroll=True,
|
||||
)
|
||||
|
||||
# Read the generated module
|
||||
module_file = Path(tmpdir) / "top.sv"
|
||||
content = module_file.read_text()
|
||||
|
||||
# Should have individual interfaces for each element in the 2x3 array
|
||||
# Format should be m_apb_matrix_0_0, m_apb_matrix_0_1, ..., m_apb_matrix_1_2
|
||||
assert "m_apb_matrix_0_0" in content
|
||||
assert "m_apb_matrix_0_1" in content
|
||||
assert "m_apb_matrix_0_2" in content
|
||||
assert "m_apb_matrix_1_0" in content
|
||||
assert "m_apb_matrix_1_1" in content
|
||||
assert "m_apb_matrix_1_2" in content
|
||||
|
||||
# Should NOT have array dimensions on any of the unrolled interfaces
|
||||
for i in range(2):
|
||||
for j in range(3):
|
||||
assert f"m_apb_matrix_{i}_{j} [" not in content
|
||||
@@ -1,262 +0,0 @@
|
||||
"""Tests for utility functions."""
|
||||
|
||||
|
||||
|
||||
import pytest
|
||||
from systemrdl import RDLCompiler
|
||||
from systemrdl.node import AddrmapNode
|
||||
|
||||
from peakrdl_busdecoder.utils import clog2, get_indexed_path, is_pow2, roundup_pow2
|
||||
|
||||
|
||||
class TestMathUtils:
|
||||
"""Test mathematical utility functions."""
|
||||
|
||||
def test_clog2_basic(self):
|
||||
"""Test clog2 function with basic values."""
|
||||
assert clog2(1) == 0
|
||||
assert clog2(2) == 1
|
||||
assert clog2(3) == 2
|
||||
assert clog2(4) == 2
|
||||
assert clog2(5) == 3
|
||||
assert clog2(8) == 3
|
||||
assert clog2(9) == 4
|
||||
assert clog2(16) == 4
|
||||
assert clog2(17) == 5
|
||||
assert clog2(32) == 5
|
||||
assert clog2(33) == 6
|
||||
assert clog2(64) == 6
|
||||
assert clog2(128) == 7
|
||||
assert clog2(256) == 8
|
||||
assert clog2(1024) == 10
|
||||
|
||||
def test_is_pow2_true_cases(self):
|
||||
"""Test is_pow2 returns True for powers of 2."""
|
||||
assert is_pow2(1) is True
|
||||
assert is_pow2(2) is True
|
||||
assert is_pow2(4) is True
|
||||
assert is_pow2(8) is True
|
||||
assert is_pow2(16) is True
|
||||
assert is_pow2(32) is True
|
||||
assert is_pow2(64) is True
|
||||
assert is_pow2(128) is True
|
||||
assert is_pow2(256) is True
|
||||
assert is_pow2(512) is True
|
||||
assert is_pow2(1024) is True
|
||||
|
||||
def test_is_pow2_false_cases(self):
|
||||
"""Test is_pow2 returns False for non-powers of 2."""
|
||||
assert is_pow2(0) is False
|
||||
assert is_pow2(3) is False
|
||||
assert is_pow2(5) is False
|
||||
assert is_pow2(6) is False
|
||||
assert is_pow2(7) is False
|
||||
assert is_pow2(9) is False
|
||||
assert is_pow2(10) is False
|
||||
assert is_pow2(15) is False
|
||||
assert is_pow2(17) is False
|
||||
assert is_pow2(100) is False
|
||||
assert is_pow2(255) is False
|
||||
assert is_pow2(1000) is False
|
||||
|
||||
def test_roundup_pow2_already_power_of_2(self):
|
||||
"""Test roundup_pow2 with values that are already powers of 2."""
|
||||
assert roundup_pow2(1) == 1
|
||||
assert roundup_pow2(2) == 2
|
||||
assert roundup_pow2(4) == 4
|
||||
assert roundup_pow2(8) == 8
|
||||
assert roundup_pow2(16) == 16
|
||||
assert roundup_pow2(32) == 32
|
||||
assert roundup_pow2(64) == 64
|
||||
assert roundup_pow2(128) == 128
|
||||
assert roundup_pow2(256) == 256
|
||||
|
||||
def test_roundup_pow2_non_power_of_2(self):
|
||||
"""Test roundup_pow2 with values that are not powers of 2."""
|
||||
assert roundup_pow2(3) == 4
|
||||
assert roundup_pow2(5) == 8
|
||||
assert roundup_pow2(6) == 8
|
||||
assert roundup_pow2(7) == 8
|
||||
assert roundup_pow2(9) == 16
|
||||
assert roundup_pow2(15) == 16
|
||||
assert roundup_pow2(17) == 32
|
||||
assert roundup_pow2(31) == 32
|
||||
assert roundup_pow2(33) == 64
|
||||
assert roundup_pow2(100) == 128
|
||||
assert roundup_pow2(255) == 256
|
||||
assert roundup_pow2(257) == 512
|
||||
|
||||
|
||||
class TestGetIndexedPath:
|
||||
"""Test get_indexed_path function."""
|
||||
|
||||
def test_simple_path(self, compile_rdl):
|
||||
"""Test simple path without arrays."""
|
||||
rdl_source = """
|
||||
addrmap my_addrmap {
|
||||
reg {
|
||||
field {} data;
|
||||
} my_reg;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="my_addrmap")
|
||||
# Get the register node by iterating through children
|
||||
reg_node = None
|
||||
for child in top.children():
|
||||
if child.inst_name == "my_reg":
|
||||
reg_node = child
|
||||
break
|
||||
|
||||
assert reg_node is not None
|
||||
path = get_indexed_path(top, reg_node)
|
||||
assert path == "my_reg"
|
||||
|
||||
def test_nested_path(self, compile_rdl):
|
||||
"""Test nested path without arrays."""
|
||||
rdl_source = """
|
||||
addrmap inner_map {
|
||||
reg {
|
||||
field {} data;
|
||||
} my_reg;
|
||||
};
|
||||
|
||||
addrmap my_addrmap {
|
||||
inner_map inner;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="my_addrmap")
|
||||
# Navigate to the nested register
|
||||
inner_node = None
|
||||
for child in top.children():
|
||||
if child.inst_name == "inner":
|
||||
inner_node = child
|
||||
break
|
||||
assert inner_node is not None
|
||||
|
||||
reg_node = None
|
||||
for child in inner_node.children():
|
||||
if child.inst_name == "my_reg":
|
||||
reg_node = child
|
||||
break
|
||||
assert reg_node is not None
|
||||
|
||||
path = get_indexed_path(top, reg_node)
|
||||
assert path == "inner.my_reg"
|
||||
|
||||
def test_array_path(self, compile_rdl):
|
||||
"""Test path with array indices."""
|
||||
rdl_source = """
|
||||
addrmap my_addrmap {
|
||||
reg {
|
||||
field {} data;
|
||||
} my_reg[4];
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="my_addrmap")
|
||||
reg_node = None
|
||||
for child in top.children():
|
||||
if child.inst_name == "my_reg":
|
||||
reg_node = child
|
||||
break
|
||||
assert reg_node is not None
|
||||
|
||||
path = get_indexed_path(top, reg_node)
|
||||
assert path == "my_reg[i0]"
|
||||
|
||||
def test_multidimensional_array_path(self, compile_rdl):
|
||||
"""Test path with multidimensional arrays."""
|
||||
rdl_source = """
|
||||
addrmap my_addrmap {
|
||||
reg {
|
||||
field {} data;
|
||||
} my_reg[2][3];
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="my_addrmap")
|
||||
reg_node = None
|
||||
for child in top.children():
|
||||
if child.inst_name == "my_reg":
|
||||
reg_node = child
|
||||
break
|
||||
assert reg_node is not None
|
||||
|
||||
path = get_indexed_path(top, reg_node)
|
||||
assert path == "my_reg[i0][i1]"
|
||||
|
||||
def test_nested_array_path(self, compile_rdl):
|
||||
"""Test path with nested arrays."""
|
||||
rdl_source = """
|
||||
addrmap inner_map {
|
||||
reg {
|
||||
field {} data;
|
||||
} my_reg[2];
|
||||
};
|
||||
|
||||
addrmap my_addrmap {
|
||||
inner_map inner[3];
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="my_addrmap")
|
||||
# Navigate to the nested register
|
||||
inner_node = None
|
||||
for child in top.children():
|
||||
if child.inst_name == "inner":
|
||||
inner_node = child
|
||||
break
|
||||
assert inner_node is not None
|
||||
|
||||
reg_node = None
|
||||
for child in inner_node.children():
|
||||
if child.inst_name == "my_reg":
|
||||
reg_node = child
|
||||
break
|
||||
assert reg_node is not None
|
||||
|
||||
path = get_indexed_path(top, reg_node)
|
||||
assert path == "inner[i0].my_reg[i1]"
|
||||
|
||||
def test_custom_indexer(self, compile_rdl):
|
||||
"""Test path with custom indexer name."""
|
||||
rdl_source = """
|
||||
addrmap my_addrmap {
|
||||
reg {
|
||||
field {} data;
|
||||
} my_reg[4];
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="my_addrmap")
|
||||
reg_node = None
|
||||
for child in top.children():
|
||||
if child.inst_name == "my_reg":
|
||||
reg_node = child
|
||||
break
|
||||
assert reg_node is not None
|
||||
|
||||
path = get_indexed_path(top, reg_node, indexer="idx")
|
||||
assert path == "my_reg[idx0]"
|
||||
|
||||
def test_skip_kw_filter(self, compile_rdl):
|
||||
"""Test path with keyword filtering skipped."""
|
||||
rdl_source = """
|
||||
addrmap my_addrmap {
|
||||
reg {
|
||||
field {} data;
|
||||
} always_reg;
|
||||
};
|
||||
"""
|
||||
top = compile_rdl(rdl_source, top="my_addrmap")
|
||||
reg_node = None
|
||||
for child in top.children():
|
||||
if child.inst_name == "always_reg":
|
||||
reg_node = child
|
||||
break
|
||||
assert reg_node is not None
|
||||
|
||||
# With keyword filter (default) - SystemRDL identifiers can use keywords but SV can't
|
||||
path = get_indexed_path(top, reg_node)
|
||||
# The path should contain always_reg
|
||||
assert "always_reg" in path
|
||||
|
||||
# Without keyword filter
|
||||
path = get_indexed_path(top, reg_node, skip_kw_filter=True)
|
||||
assert path == "always_reg"
|
||||
Reference in New Issue
Block a user