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Refactor tests (better grouping + cocotb support) (#15)

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* initial refactor

* fix cocotb tests

* fix typecheck

* install verilator
This commit is contained in:
Arnav Sacheti
2025-10-26 17:56:35 -07:00
committed by GitHub
parent 93276ff616
commit b1f1bf983a
66 changed files with 1734 additions and 2963 deletions
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75
tests/unit/test_external_nested.py
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@@ -1,79 +1,16 @@
"""Test handling of external nested addressable components."""
from collections.abc import Callable
from pathlib import Path
from tempfile import TemporaryDirectory
import pytest
from systemrdl.node import AddrmapNode
from peakrdl_busdecoder import BusDecoderExporter
from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
@pytest.fixture
def external_nested_rdl(compile_rdl):
"""Create an RDL design with external nested addressable components.
This tests the scenario where an addrmap contains external children
that themselves have external addressable children.
The decoder should only generate select signals for the top-level
external children, not their internal structure.
"""
rdl_source = """
mem queue_t {
name = "Queue";
mementries = 1024;
memwidth = 64;
};
addrmap port_t {
name = "Port";
desc = "";
external queue_t common[3] @ 0x0 += 0x2000;
external queue_t response @ 0x6000;
};
addrmap buffer_t {
name = "Buffer";
desc = "";
port_t multicast @ 0x0;
port_t port [16] @ 0x8000 += 0x8000;
};
"""
return compile_rdl(rdl_source, top="buffer_t")
@pytest.fixture
def nested_addrmap_rdl(compile_rdl):
"""Create an RDL design with nested non-external addrmaps for testing depth control."""
rdl_source = """
addrmap level2 {
reg {
field { sw=rw; hw=r; } data2[31:0];
} reg2 @ 0x0;
reg {
field { sw=rw; hw=r; } data2b[31:0];
} reg2b @ 0x4;
};
addrmap level1 {
reg {
field { sw=rw; hw=r; } data1[31:0];
} reg1 @ 0x0;
level2 inner2 @ 0x10;
};
addrmap level0 {
level1 inner1 @ 0x0;
};
"""
return compile_rdl(rdl_source, top="level0")
def test_external_nested_components_generate_correct_decoder(external_nested_rdl):
def test_external_nested_components_generate_correct_decoder(external_nested_rdl: AddrmapNode) -> None:
"""Test that external nested components generate correct decoder logic.
The decoder should:
@@ -109,7 +46,7 @@ def test_external_nested_components_generate_correct_decoder(external_nested_rdl
assert "logic [15:0]port;" in content
def test_external_nested_components_generate_correct_interfaces(external_nested_rdl):
def test_external_nested_components_generate_correct_interfaces(external_nested_rdl: AddrmapNode) -> None:
"""Test that external nested components generate correct interface ports.
The module should have:
@@ -140,7 +77,7 @@ def test_external_nested_components_generate_correct_interfaces(external_nested_
assert "m_apb_response" not in content
def test_non_external_nested_components_are_descended(compile_rdl):
def test_non_external_nested_components_are_descended(compile_rdl: Callable[..., AddrmapNode]) -> None:
"""Test that non-external nested components are still descended into.
This is a regression test to ensure we didn't break normal nested
@@ -175,7 +112,7 @@ def test_non_external_nested_components_are_descended(compile_rdl):
assert "inner_reg" in content
def test_max_decode_depth_parameter_exists(compile_rdl):
def test_max_decode_depth_parameter_exists(compile_rdl: Callable[..., AddrmapNode]) -> None:
"""Test that max_decode_depth parameter can be set."""
rdl_source = """
addrmap simple {