From b2fd006f7f8bd00ec56e859e2dbd29b4b290da7f Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sat, 22 Nov 2025 16:34:52 -0800
Subject: [PATCH] Gate assertions behind "PEAKRDL_ASSERTIONS define"

---
 src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv          | 2 ++
 src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_tmpl.sv | 2 ++
 src/peakrdl_busdecoder/cpuif/taxi_apb/taxi_apb_tmpl.sv  | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv b/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
index 025a0a7..f4f9e0b 100644
--- a/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
+++ b/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv
@@ -6,8 +6,10 @@
         assert_bad_data_width: assert($bits({{cpuif.signal("PWDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
             else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("PWDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
     end
+    `ifdef PEAKRDL_ASSERTIONS
     assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("PSEL")}} && {{cpuif.signal("PWRITE")}} |-> ##1 ({{cpuif.signal("PREADY")}} || {{cpuif.signal("PSLVERR")}}))
         else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+    `endif
 `endif
 {%- endif %}
 
diff --git a/src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_tmpl.sv b/src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_tmpl.sv
index a7be528..b177561 100644
--- a/src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_tmpl.sv
+++ b/src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_tmpl.sv
@@ -15,6 +15,7 @@
                         $bits({{cpuif.signal("WDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
     end
 
+    `ifdef PEAKRDL_ASSERTIONS
     // Simple handshake sanity (one-cycle implication; relax/adjust as needed)
     assert_rd_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}})
         {{cpuif.signal("RVALID")}} |-> (^{{cpuif.signal("RRESP")}} !== 1'bx))
@@ -23,6 +24,7 @@
     assert_wr_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}})
         {{cpuif.signal("BVALID")}} |-> (^{{cpuif.signal("BRESP")}} !== 1'bx))
             else $error("BRESP must be a legal AXI response when BVALID is high");
+    `endif
 `endif
 {% endif -%}
 
diff --git a/src/peakrdl_busdecoder/cpuif/taxi_apb/taxi_apb_tmpl.sv b/src/peakrdl_busdecoder/cpuif/taxi_apb/taxi_apb_tmpl.sv
index c1b1d9f..8c6c908 100644
--- a/src/peakrdl_busdecoder/cpuif/taxi_apb/taxi_apb_tmpl.sv
+++ b/src/peakrdl_busdecoder/cpuif/taxi_apb/taxi_apb_tmpl.sv
@@ -6,8 +6,10 @@
         assert_bad_data_width: assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
             else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("pwdata")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
     end
+    `ifdef PEAKRDL_ASSERTIONS
     assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("psel")}} && {{cpuif.signal("pwrite")}} |-> ##1 ({{cpuif.signal("pready")}} || {{cpuif.signal("pslverr")}}))
         else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+    `endif
 `endif
 {%- endif %}