bslathi19/PeakRDL-BusDecoder
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regblock -> busdecoder

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Arnav Sacheti
2025-10-10 22:30:59 -07:00
parent 9bf5cd1e68
commit b4f9eaff71
78 changed files with 904 additions and 705 deletions
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tests/lib/synthesizers/vivado_scripts/run.tcl
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@@ -25,7 +25,7 @@ set_msg_config -severity {CRITICAL WARNING} -new_severity "ERROR"
set_part [lindex [get_parts] 0]
read_verilog -sv $files
read_xdc $this_dir/constr.xdc
synth_design -top regblock -mode out_of_context
synth_design -top busdecoder -mode out_of_context
#write_checkpoint -force synth.dcp