decoder compiles

src/peakrdl_busdecoder/validate_design.py

@@ -1,7 +1,7 @@
 from typing import TYPE_CHECKING
 
 from systemrdl.node import AddressableNode, AddrmapNode, FieldNode, Node, RegfileNode, RegNode, SignalNode
-from systemrdl.rdltypes import PropertyReference
+from systemrdl.rdltypes.references import PropertyReference
 from systemrdl.walker import RDLListener, RDLWalker, WalkerAction
 
 from .utils import is_pow2, ref_is_internal, roundup_pow2
@@ -148,21 +148,6 @@ class DesignValidator(RDLListener):
                     node.inst.inst_src_ref,
                 )
 
-        # Check for unsynthesizable reset
-        reset = node.get_property("reset")
-        if not (reset is None or isinstance(reset, int)):
-            # Has reset that is not a constant value
-            resetsignal = node.get_property("resetsignal")
-            if resetsignal:
-                is_async_reset = resetsignal.get_property("async")
-            else:
-                is_async_reset = self.ds.default_reset_async
-
-            if is_async_reset:
-                self.msg.error(
-                    "A field that uses an asynchronous reset cannot use a dynamic reset value. This is not synthesizable.",
-                    node.inst.inst_src_ref,
-                )
 
     def exit_AddressableComponent(self, node: AddressableNode) -> None:
         if not isinstance(node, RegNode):