This commit is contained in:
Arnav Sacheti
2025-10-27 22:53:38 -07:00
parent d7481e71ba
commit bbbeab85c5
12 changed files with 1193 additions and 322 deletions

View File

@@ -1,5 +1,8 @@
"""Pytest wrapper launching the APB4 cocotb smoke test."""
"""Pytest wrapper launching the APB4 cocotb smoke tests."""
from __future__ import annotations
import json
from pathlib import Path
import pytest
@@ -11,20 +14,25 @@ try: # pragma: no cover - optional dependency shim
except ImportError: # pragma: no cover
from cocotb_tools.runner import get_runner
from tests.cocotb_lib.utils import compile_rdl_and_export, get_verilog_sources
from tests.cocotb_lib import RDL_CASES
from tests.cocotb_lib.utils import get_verilog_sources, prepare_cpuif_case
@pytest.mark.simulation
@pytest.mark.verilator
def test_apb4_smoke(tmp_path: Path) -> None:
"""Compile the APB4 design and execute the cocotb smoke test."""
@pytest.mark.parametrize(("rdl_file", "top_name"), RDL_CASES, ids=[case[1] for case in RDL_CASES])
def test_apb4_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
"""Compile each APB4 design variant and execute the cocotb smoke test."""
repo_root = Path(__file__).resolve().parents[4]
rdl_path = repo_root / "tests" / "cocotb_lib" / rdl_file
build_root = tmp_path / top_name
module_path, package_path = compile_rdl_and_export(
str(repo_root / "tests" / "cocotb_lib" / "multiple_reg.rdl"),
"multi_reg",
tmp_path,
module_path, package_path, config = prepare_cpuif_case(
str(rdl_path),
top_name,
build_root,
cpuif_cls=APB4CpuifFlat,
control_signal="PSEL",
)
sources = get_verilog_sources(
@@ -34,17 +42,18 @@ def test_apb4_smoke(tmp_path: Path) -> None:
)
runner = get_runner("verilator")
build_dir = tmp_path / "sim_build"
sim_build = build_root / "sim_build"
runner.build(
sources=sources,
hdl_toplevel=module_path.stem,
build_dir=build_dir,
build_dir=sim_build,
)
runner.test(
hdl_toplevel=module_path.stem,
test_module="tests.cocotb.apb4.smoke.test_register_access",
build_dir=build_dir,
log_file=str(tmp_path / "sim.log"),
build_dir=sim_build,
log_file=str(build_root / "simulation.log"),
extra_env={"RDL_TEST_CONFIG": json.dumps(config)},
)