Dev/downsize apb paddr (#27)

* Downsize paddr bits

* Updated Test suite to use offset aligned address

* fix for apb3 and axi4lite

* modified structure to pass hierarchy information

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Co-authored-by: Byron Lathi <bslathi19@gmail.com>

src/peakrdl_busdecoder/cpuif/apb3/apb3_interface.py

@@ -2,6 +2,7 @@
 
 from systemrdl.node import AddressableNode
 
+from ...utils import clog2
 from ..interface import FlatInterface, SVInterface
 
 
@@ -48,7 +49,7 @@ class APB3FlatInterface(FlatInterface):
             f"output logic {self.signal('PSEL', child)}",
             f"output logic {self.signal('PENABLE', child)}",
             f"output logic {self.signal('PWRITE', child)}",
-            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('PADDR', child)}",
+            f"output logic [{clog2(child.size) - 1}:0] {self.signal('PADDR', child)}",
             f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('PWDATA', child)}",
             f"input  logic [{self.cpuif.data_width - 1}:0] {self.signal('PRDATA', child)}",
             f"input  logic {self.signal('PREADY', child)}",