bslathi19/PeakRDL-BusDecoder
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Dev/downsize apb paddr (#27)

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* Downsize paddr bits

* Updated Test suite to use offset aligned address

* fix for apb3 and axi4lite

* modified structure to pass hierarchy information

---------

Co-authored-by: Byron Lathi <bslathi19@gmail.com>
This commit is contained in:
Arnav Sacheti
2025-12-04 21:31:44 -08:00
committed by GitHub
parent 9f41487430
commit c63b2cbab2
16 changed files with 89 additions and 26 deletions
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16
src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py
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@@ -1,8 +1,10 @@
from collections import deque
from typing import TYPE_CHECKING, overload
from systemrdl.node import AddressableNode
from ...utils import get_indexed_path
from ...sv_int import SVInt
from ...utils import clog2, get_indexed_path
from ..base_cpuif import BaseCpuif
from .axi4_lite_interface import AXI4LiteFlatInterface
@@ -35,15 +37,21 @@ class AXI4LiteCpuifFlat(BaseCpuif):
def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
return self._interface.signal(signal, node, indexer)
def fanout(self, node: AddressableNode) -> str:
def fanout(self, node: AddressableNode, array_stack: deque[int]) -> str:
fanout: dict[str, str] = {}
waddr_comp = [f"{self.signal('AWADDR')}"]
raddr_comp = [f"{self.signal('ARADDR')}"]
for i, stride in enumerate(array_stack):
offset = f"(gi{i}*{SVInt(stride, self.addr_width)})"
waddr_comp.append(offset)
raddr_comp.append(offset)
wr_sel = f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
rd_sel = f"cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
# Write address channel
fanout[self.signal("AWVALID", node, "gi")] = wr_sel
fanout[self.signal("AWADDR", node, "gi")] = self.signal("AWADDR")
fanout[self.signal("AWADDR", node, "gi")] = f"{{{'-'.join(waddr_comp)}}}[{clog2(node.size) - 1}:0]"
fanout[self.signal("AWPROT", node, "gi")] = self.signal("AWPROT")
# Write data channel
@@ -56,7 +64,7 @@ class AXI4LiteCpuifFlat(BaseCpuif):
# Read address channel
fanout[self.signal("ARVALID", node, "gi")] = rd_sel
fanout[self.signal("ARADDR", node, "gi")] = self.signal("ARADDR")
fanout[self.signal("ARADDR", node, "gi")] = f"{{{'-'.join(raddr_comp)}}}[{clog2(node.size) - 1}:0]"
fanout[self.signal("ARPROT", node, "gi")] = self.signal("ARPROT")
# Read data channel (master -> slave)