Dev/downsize apb paddr (#27)
* Downsize paddr bits * Updated Test suite to use offset aligned address * fix for apb3 and axi4lite * modified structure to pass hierarchy information --------- Co-authored-by: Byron Lathi <bslathi19@gmail.com>
This commit is contained in:
@@ -64,6 +64,8 @@ def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dic
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"PREADY": SignalHandle(dut, f"{prefix}_PREADY"),
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"PSLVERR": SignalHandle(dut, f"{prefix}_PSLVERR"),
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},
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"inst_size": master["inst_size"],
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"inst_address": master["inst_address"],
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}
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table[master["inst_name"]] = entry
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return table
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@@ -125,11 +127,16 @@ async def test_apb3_address_decoding(dut) -> None:
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slave.PSEL.value = 1
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slave.PENABLE.value = 1
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dut._log.info(
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f"Starting transaction {txn['label']} to {master_name}{index} at address 0x{address:08X}"
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)
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master_address = (address - entry["inst_address"]) % entry["inst_size"]
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await Timer(1, units="ns")
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assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
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assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write direction"
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assert _get_int(entry["outputs"]["PADDR"], index) == address, (
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assert _get_int(entry["outputs"]["PADDR"], index) == master_address, (
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f"{master_name} must receive write address"
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)
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assert _get_int(entry["outputs"]["PWDATA"], index) == write_data, (
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@@ -172,7 +179,7 @@ async def test_apb3_address_decoding(dut) -> None:
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assert _get_int(entry["outputs"]["PWRITE"], index) == 0, (
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f"{master_name} should clear write during read"
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)
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assert _get_int(entry["outputs"]["PADDR"], index) == address, (
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assert _get_int(entry["outputs"]["PADDR"], index) == master_address, (
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f"{master_name} must receive read address"
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)
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@@ -3,6 +3,7 @@
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from __future__ import annotations
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import json
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import logging
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import os
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from typing import Any, Iterable
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@@ -71,6 +72,8 @@ def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dic
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"PREADY": SignalHandle(dut, f"{port_prefix}_PREADY"),
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"PSLVERR": SignalHandle(dut, f"{port_prefix}_PSLVERR"),
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},
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"inst_size": master["inst_size"],
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"inst_address": master["inst_address"],
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}
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table[master["inst_name"]] = entry
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return table
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@@ -138,11 +141,16 @@ async def test_apb4_address_decoding(dut) -> None:
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slave.PSEL.value = 1
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slave.PENABLE.value = 1
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dut._log.info(
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f"Starting transaction {txn['label']} to {master_name}{index} at address 0x{address:08X}"
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)
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master_address = (address - entry["inst_address"]) % entry["inst_size"]
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await Timer(1, units="ns")
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assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
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assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write intent"
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assert _get_int(entry["outputs"]["PADDR"], index) == address, (
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assert _get_int(entry["outputs"]["PADDR"], index) == master_address, (
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f"{master_name} must receive write address"
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)
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assert _get_int(entry["outputs"]["PWDATA"], index) == write_data, (
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@@ -189,7 +197,7 @@ async def test_apb4_address_decoding(dut) -> None:
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assert _get_int(entry["outputs"]["PWRITE"], index) == 0, (
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f"{master_name} should deassert write for reads"
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)
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assert _get_int(entry["outputs"]["PADDR"], index) == address, (
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assert _get_int(entry["outputs"]["PADDR"], index) == master_address, (
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f"{master_name} must receive read address"
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)
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@@ -3,6 +3,7 @@
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from __future__ import annotations
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import json
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import logging
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from pathlib import Path
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import logging
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@@ -28,6 +29,9 @@ def test_apb4_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
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rdl_path = repo_root / "tests" / "cocotb_lib" / "rdl" / rdl_file
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build_root = tmp_path / top_name
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logging.info(f"Running APB4 smoke test for {rdl_path} with top {top_name}")
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logging.info(f"Build root: {build_root}")
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module_path, package_path, config = prepare_cpuif_case(
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str(rdl_path),
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top_name,
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@@ -83,4 +87,4 @@ def test_apb4_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
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=== End Simulation Log ===
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""")
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if e.code != 0:
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raise
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raise e
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@@ -84,6 +84,8 @@ def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dic
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"RDATA": SignalHandle(dut, f"{prefix}_RDATA"),
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"RRESP": SignalHandle(dut, f"{prefix}_RRESP"),
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},
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"inst_size": master["inst_size"],
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"inst_address": master["inst_address"],
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}
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table[master["inst_name"]] = entry
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return table
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@@ -156,10 +158,17 @@ async def test_axi4lite_address_decoding(dut) -> None:
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slave.WVALID.value = 1
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slave.BREADY.value = 1
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dut._log.info(
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f"Starting transaction {txn['label']} to {master_name}{index} at address 0x{address:08X}"
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)
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master_address = (address - entry["inst_address"]) % entry["inst_size"]
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await Timer(1, units="ns")
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assert _get_int(entry["outputs"]["AWVALID"], index) == 1, f"{master_name} should see AWVALID asserted"
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assert _get_int(entry["outputs"]["AWADDR"], index) == address, f"{master_name} must receive AWADDR"
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assert _get_int(entry["outputs"]["AWADDR"], index) == master_address, (
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f"{master_name} must receive AWADDR"
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)
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assert _get_int(entry["outputs"]["WVALID"], index) == 1, f"{master_name} should see WVALID asserted"
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assert _get_int(entry["outputs"]["WDATA"], index) == write_data, f"{master_name} must receive WDATA"
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assert _get_int(entry["outputs"]["WSTRB"], index) == strobe_mask, f"{master_name} must receive WSTRB"
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@@ -193,7 +202,9 @@ async def test_axi4lite_address_decoding(dut) -> None:
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await Timer(1, units="ns")
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assert _get_int(entry["outputs"]["ARVALID"], index) == 1, f"{master_name} should assert ARVALID"
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assert _get_int(entry["outputs"]["ARADDR"], index) == address, f"{master_name} must receive ARADDR"
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assert _get_int(entry["outputs"]["ARADDR"], index) == master_address, (
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f"{master_name} must receive ARADDR"
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)
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for other_name, other_idx in _all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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@@ -223,6 +223,8 @@ def _build_case_config(
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"is_array": bool(child.is_array),
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"dimensions": list(child.array_dimensions or []),
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"indices": set(),
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"inst_size": child.array_stride if child.is_array else child.size,
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"inst_address": child.raw_absolute_address,
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}
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# Map each register to its top-level master and collect addresses
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@@ -252,6 +254,8 @@ def _build_case_config(
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"is_array": bool(master.is_array),
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"dimensions": list(master.array_dimensions or []),
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"indices": set(),
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"inst_size": master.array_stride if master.is_array else master.size,
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"inst_address": master.raw_absolute_address,
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}
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idx_tuple = tuple(master.current_idx or [])
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@@ -279,6 +283,8 @@ def _build_case_config(
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"is_array": entry["is_array"],
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"dimensions": entry["dimensions"],
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"indices": entry["indices"],
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"inst_size": entry["inst_size"],
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"inst_address": entry["inst_address"],
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}
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)
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