Dev/downsize apb paddr (#27)

* Downsize paddr bits

* Updated Test suite to use offset aligned address

* fix for apb3 and axi4lite

* modified structure to pass hierarchy information

---------

Co-authored-by: Byron Lathi <bslathi19@gmail.com>
This commit is contained in:
Arnav Sacheti
2025-12-04 21:31:44 -08:00
committed by GitHub
parent 9f41487430
commit c63b2cbab2
16 changed files with 89 additions and 26 deletions

View File

@@ -64,6 +64,8 @@ def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dic
"PREADY": SignalHandle(dut, f"{prefix}_PREADY"),
"PSLVERR": SignalHandle(dut, f"{prefix}_PSLVERR"),
},
"inst_size": master["inst_size"],
"inst_address": master["inst_address"],
}
table[master["inst_name"]] = entry
return table
@@ -125,11 +127,16 @@ async def test_apb3_address_decoding(dut) -> None:
slave.PSEL.value = 1
slave.PENABLE.value = 1
dut._log.info(
f"Starting transaction {txn['label']} to {master_name}{index} at address 0x{address:08X}"
)
master_address = (address - entry["inst_address"]) % entry["inst_size"]
await Timer(1, units="ns")
assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write direction"
assert _get_int(entry["outputs"]["PADDR"], index) == address, (
assert _get_int(entry["outputs"]["PADDR"], index) == master_address, (
f"{master_name} must receive write address"
)
assert _get_int(entry["outputs"]["PWDATA"], index) == write_data, (
@@ -172,7 +179,7 @@ async def test_apb3_address_decoding(dut) -> None:
assert _get_int(entry["outputs"]["PWRITE"], index) == 0, (
f"{master_name} should clear write during read"
)
assert _get_int(entry["outputs"]["PADDR"], index) == address, (
assert _get_int(entry["outputs"]["PADDR"], index) == master_address, (
f"{master_name} must receive read address"
)

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@@ -3,6 +3,7 @@
from __future__ import annotations
import json
import logging
import os
from typing import Any, Iterable
@@ -71,6 +72,8 @@ def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dic
"PREADY": SignalHandle(dut, f"{port_prefix}_PREADY"),
"PSLVERR": SignalHandle(dut, f"{port_prefix}_PSLVERR"),
},
"inst_size": master["inst_size"],
"inst_address": master["inst_address"],
}
table[master["inst_name"]] = entry
return table
@@ -138,11 +141,16 @@ async def test_apb4_address_decoding(dut) -> None:
slave.PSEL.value = 1
slave.PENABLE.value = 1
dut._log.info(
f"Starting transaction {txn['label']} to {master_name}{index} at address 0x{address:08X}"
)
master_address = (address - entry["inst_address"]) % entry["inst_size"]
await Timer(1, units="ns")
assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write intent"
assert _get_int(entry["outputs"]["PADDR"], index) == address, (
assert _get_int(entry["outputs"]["PADDR"], index) == master_address, (
f"{master_name} must receive write address"
)
assert _get_int(entry["outputs"]["PWDATA"], index) == write_data, (
@@ -189,7 +197,7 @@ async def test_apb4_address_decoding(dut) -> None:
assert _get_int(entry["outputs"]["PWRITE"], index) == 0, (
f"{master_name} should deassert write for reads"
)
assert _get_int(entry["outputs"]["PADDR"], index) == address, (
assert _get_int(entry["outputs"]["PADDR"], index) == master_address, (
f"{master_name} must receive read address"
)

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@@ -3,6 +3,7 @@
from __future__ import annotations
import json
import logging
from pathlib import Path
import logging
@@ -28,6 +29,9 @@ def test_apb4_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
rdl_path = repo_root / "tests" / "cocotb_lib" / "rdl" / rdl_file
build_root = tmp_path / top_name
logging.info(f"Running APB4 smoke test for {rdl_path} with top {top_name}")
logging.info(f"Build root: {build_root}")
module_path, package_path, config = prepare_cpuif_case(
str(rdl_path),
top_name,
@@ -83,4 +87,4 @@ def test_apb4_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
=== End Simulation Log ===
""")
if e.code != 0:
raise
raise e

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@@ -84,6 +84,8 @@ def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dic
"RDATA": SignalHandle(dut, f"{prefix}_RDATA"),
"RRESP": SignalHandle(dut, f"{prefix}_RRESP"),
},
"inst_size": master["inst_size"],
"inst_address": master["inst_address"],
}
table[master["inst_name"]] = entry
return table
@@ -156,10 +158,17 @@ async def test_axi4lite_address_decoding(dut) -> None:
slave.WVALID.value = 1
slave.BREADY.value = 1
dut._log.info(
f"Starting transaction {txn['label']} to {master_name}{index} at address 0x{address:08X}"
)
master_address = (address - entry["inst_address"]) % entry["inst_size"]
await Timer(1, units="ns")
assert _get_int(entry["outputs"]["AWVALID"], index) == 1, f"{master_name} should see AWVALID asserted"
assert _get_int(entry["outputs"]["AWADDR"], index) == address, f"{master_name} must receive AWADDR"
assert _get_int(entry["outputs"]["AWADDR"], index) == master_address, (
f"{master_name} must receive AWADDR"
)
assert _get_int(entry["outputs"]["WVALID"], index) == 1, f"{master_name} should see WVALID asserted"
assert _get_int(entry["outputs"]["WDATA"], index) == write_data, f"{master_name} must receive WDATA"
assert _get_int(entry["outputs"]["WSTRB"], index) == strobe_mask, f"{master_name} must receive WSTRB"
@@ -193,7 +202,9 @@ async def test_axi4lite_address_decoding(dut) -> None:
await Timer(1, units="ns")
assert _get_int(entry["outputs"]["ARVALID"], index) == 1, f"{master_name} should assert ARVALID"
assert _get_int(entry["outputs"]["ARADDR"], index) == address, f"{master_name} must receive ARADDR"
assert _get_int(entry["outputs"]["ARADDR"], index) == master_address, (
f"{master_name} must receive ARADDR"
)
for other_name, other_idx in _all_index_pairs(masters):
if other_name == master_name and other_idx == index:

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@@ -223,6 +223,8 @@ def _build_case_config(
"is_array": bool(child.is_array),
"dimensions": list(child.array_dimensions or []),
"indices": set(),
"inst_size": child.array_stride if child.is_array else child.size,
"inst_address": child.raw_absolute_address,
}
# Map each register to its top-level master and collect addresses
@@ -252,6 +254,8 @@ def _build_case_config(
"is_array": bool(master.is_array),
"dimensions": list(master.array_dimensions or []),
"indices": set(),
"inst_size": master.array_stride if master.is_array else master.size,
"inst_address": master.raw_absolute_address,
}
idx_tuple = tuple(master.current_idx or [])
@@ -279,6 +283,8 @@ def _build_case_config(
"is_array": entry["is_array"],
"dimensions": entry["dimensions"],
"indices": entry["indices"],
"inst_size": entry["inst_size"],
"inst_address": entry["inst_address"],
}
)