bslathi19/PeakRDL-BusDecoder
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set cpuif_data_width for non-external components (#42)

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* set cpuif_data_width for non-external components

* update tests to actually work now

* version bump
This commit is contained in:
Arnav Sacheti
2026-02-03 21:58:45 -08:00
committed by GitHub
parent 36ec8b9715
commit c7b6c9e5ef
10 changed files with 226 additions and 5 deletions
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2
tests/cocotb_lib/__init__.py
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@@ -5,6 +5,8 @@ RDL_CASES: list[tuple[str, str]] = [
("multiple_reg.rdl", "multi_reg"),
("deep_hierarchy.rdl", "deep_hierarchy"),
("wide_status.rdl", "wide_status"),
("wide_access_64.rdl", "wide_access_64"),
("wide_access_128.rdl", "wide_access_128"),
("variable_layout.rdl", "variable_layout"),
("asymmetric_bus.rdl", "asymmetric_bus"),
]

10
tests/cocotb_lib/rdl/asymmetric_bus.rdl
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@@ -73,6 +73,7 @@ addrmap asymmetric_bus {
reg {
regwidth = 64;
accesswidth = 32;
field {
sw = rw;
hw = rw;
@@ -88,11 +89,18 @@ addrmap asymmetric_bus {
reg {
regwidth = 128;
accesswidth = 32;
field {
sw = rw;
hw = rw;
reset = 0x0;
} extended_id[63:0];
} extended_id_low[31:0];
field {
sw = rw;
hw = rw;
reset = 0x0;
} extended_id_high[63:32];
field {
sw = rw;

1
tests/cocotb_lib/rdl/variable_layout.rdl
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@@ -69,6 +69,7 @@ regfile slice_rf {
reg {
regwidth = 64;
accesswidth = 32;
field {
sw = r;
hw = w;

75
tests/cocotb_lib/rdl/wide_access_128.rdl Normal file
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@@ -0,0 +1,75 @@
reg payload128_reg_t {
regwidth = 128;
accesswidth = 128;
desc = "128-bit payload register.";
field {
sw = rw;
hw = rw;
reset = 0x0;
} word0[31:0];
field {
sw = rw;
hw = rw;
reset = 0x0;
} word1[63:32];
field {
sw = rw;
hw = rw;
reset = 0x0;
} word2[95:64];
field {
sw = rw;
hw = rw;
reset = 0x0;
} word3[127:96];
};
regfile block128_rf {
payload128_reg_t payload @ 0x0;
reg {
regwidth = 128;
accesswidth = 128;
field {
sw = r;
hw = w;
reset = 0x0;
} status0[31:0];
field {
sw = r;
hw = w;
reset = 0x0;
} status1[63:32];
field {
sw = r;
hw = w;
reset = 0x0;
} status2[95:64];
field {
sw = r;
hw = w;
reset = 0x0;
} status3[127:96];
} status @ 0x10;
};
addrmap wide_access_128 {
block128_rf blocks[2] @ 0x0 += 0x40;
reg {
regwidth = 64;
accesswidth = 64;
field {
sw = rw;
hw = rw;
reset = 0x0;
} id[63:0];
} id @ 0x100;
};

56
tests/cocotb_lib/rdl/wide_access_64.rdl Normal file
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@@ -0,0 +1,56 @@
reg status64_reg_t {
regwidth = 64;
accesswidth = 64;
desc = "64-bit status register.";
field {
sw = r;
hw = w;
reset = 0x0;
} status_lo[31:0];
field {
sw = r;
hw = w;
reset = 0x0;
} status_hi[63:32];
};
regfile channel64_rf {
status64_reg_t status @ 0x0;
reg {
regwidth = 64;
accesswidth = 64;
field {
sw = rw;
hw = rw;
reset = 0x1;
} enable[0:0];
field {
sw = rw;
hw = rw;
reset = 0x0;
} mode[2:1];
field {
sw = rw;
hw = rw;
reset = 0x0;
} threshold[63:3];
} control @ 0x8;
};
addrmap wide_access_64 {
channel64_rf channels[4] @ 0x0 += 0x20;
reg {
regwidth = 32;
field {
sw = rw;
hw = rw;
reset = 0x0;
} flags[31:0];
} flags @ 0x100;
};

32
tests/cocotb_lib/rdl/wide_status.rdl
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@@ -1,5 +1,6 @@
reg status_reg_t {
regwidth = 64;
accesswidth = 32;
desc = "Status register capturing wide flags and sticky bits.";
field {
@@ -7,7 +8,14 @@ reg status_reg_t {
hw = w;
onread = rclr;
reset = 0x0;
} flags[62:0];
} flags_low[31:0];
field {
sw = r;
hw = w;
onread = rclr;
reset = 0x0;
} flags_high[62:32];
field {
sw = rw;
@@ -18,6 +26,7 @@ reg status_reg_t {
reg metrics_reg_t {
regwidth = 64;
accesswidth = 32;
desc = "Metrics register pairing counters with thresholds.";
field {
@@ -40,11 +49,30 @@ addrmap wide_status {
reg {
regwidth = 128;
accesswidth = 32;
field {
sw = rw;
hw = rw;
reset = 0x0;
} configuration[127:0];
} configuration_0[31:0];
field {
sw = rw;
hw = rw;
reset = 0x0;
} configuration_1[63:32];
field {
sw = rw;
hw = rw;
reset = 0x0;
} configuration_2[95:64];
field {
sw = rw;
hw = rw;
reset = 0x0;
} configuration_3[127:96];
} configuration @ 0x800;
reg {