Fix max_decode_depth to control decoder hierarchy and port generation (#18)
* Initial plan * Fix max_decode_depth to properly control decoder hierarchy and port generation Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix test that relied on old depth behavior Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Update documentation for max_decode_depth parameter Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * fix format * Add variable_depth RDL file and smoke tests for max_decode_depth parameter Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add variable depth tests for APB3 and AXI4-Lite CPUIFs Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * fix * fix * bump --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
This commit is contained in:
Copilot
271
tests/cocotb/axi4lite/smoke/test_variable_depth.py
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271
tests/cocotb/axi4lite/smoke/test_variable_depth.py
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"""AXI4-Lite smoke tests for variable depth design testing max_decode_depth parameter."""
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import cocotb
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from cocotb.triggers import Timer
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class _AxilSlaveShim:
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def __init__(self, dut):
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prefix = "s_axil"
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self.AWREADY = getattr(dut, f"{prefix}_AWREADY")
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self.AWVALID = getattr(dut, f"{prefix}_AWVALID")
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self.AWADDR = getattr(dut, f"{prefix}_AWADDR")
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self.AWPROT = getattr(dut, f"{prefix}_AWPROT")
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self.WREADY = getattr(dut, f"{prefix}_WREADY")
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self.WVALID = getattr(dut, f"{prefix}_WVALID")
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self.WDATA = getattr(dut, f"{prefix}_WDATA")
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self.WSTRB = getattr(dut, f"{prefix}_WSTRB")
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self.BREADY = getattr(dut, f"{prefix}_BREADY")
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self.BVALID = getattr(dut, f"{prefix}_BVALID")
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self.BRESP = getattr(dut, f"{prefix}_BRESP")
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self.ARREADY = getattr(dut, f"{prefix}_ARREADY")
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self.ARVALID = getattr(dut, f"{prefix}_ARVALID")
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self.ARADDR = getattr(dut, f"{prefix}_ARADDR")
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self.ARPROT = getattr(dut, f"{prefix}_ARPROT")
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self.RREADY = getattr(dut, f"{prefix}_RREADY")
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self.RVALID = getattr(dut, f"{prefix}_RVALID")
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self.RDATA = getattr(dut, f"{prefix}_RDATA")
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self.RRESP = getattr(dut, f"{prefix}_RRESP")
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class _AxilMasterShim:
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def __init__(self, dut, base: str):
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self.AWREADY = getattr(dut, f"{base}_AWREADY")
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self.AWVALID = getattr(dut, f"{base}_AWVALID")
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self.AWADDR = getattr(dut, f"{base}_AWADDR")
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self.AWPROT = getattr(dut, f"{base}_AWPROT")
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self.WREADY = getattr(dut, f"{base}_WREADY")
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self.WVALID = getattr(dut, f"{base}_WVALID")
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self.WDATA = getattr(dut, f"{base}_WDATA")
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self.WSTRB = getattr(dut, f"{base}_WSTRB")
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self.BREADY = getattr(dut, f"{base}_BREADY")
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self.BVALID = getattr(dut, f"{base}_BVALID")
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self.BRESP = getattr(dut, f"{base}_BRESP")
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self.ARREADY = getattr(dut, f"{base}_ARREADY")
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self.ARVALID = getattr(dut, f"{base}_ARVALID")
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self.ARADDR = getattr(dut, f"{base}_ARADDR")
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self.ARPROT = getattr(dut, f"{base}_ARPROT")
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self.RREADY = getattr(dut, f"{base}_RREADY")
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self.RVALID = getattr(dut, f"{base}_RVALID")
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self.RDATA = getattr(dut, f"{base}_RDATA")
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self.RRESP = getattr(dut, f"{base}_RRESP")
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def _axil_slave(dut):
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return getattr(dut, "s_axil", None) or _AxilSlaveShim(dut)
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def _axil_master(dut, base: str):
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return getattr(dut, base, None) or _AxilMasterShim(dut, base)
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@cocotb.test()
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async def test_depth_1(dut):
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"""Test max_decode_depth=1 - should have interface for inner1 only."""
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s_axil = _axil_slave(dut)
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# At depth 1, we should have m_axil_inner1 but not deeper interfaces
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inner1 = _axil_master(dut, "m_axil_inner1")
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# Default slave side inputs
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s_axil.AWVALID.value = 0
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s_axil.AWADDR.value = 0
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s_axil.AWPROT.value = 0
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s_axil.WVALID.value = 0
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s_axil.WDATA.value = 0
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s_axil.WSTRB.value = 0
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s_axil.BREADY.value = 0
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s_axil.ARVALID.value = 0
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s_axil.ARADDR.value = 0
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s_axil.ARPROT.value = 0
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s_axil.RREADY.value = 0
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inner1.AWREADY.value = 0
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inner1.WREADY.value = 0
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inner1.BVALID.value = 0
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inner1.BRESP.value = 0
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inner1.ARREADY.value = 0
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inner1.RVALID.value = 0
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inner1.RDATA.value = 0
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inner1.RRESP.value = 0
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await Timer(1, units="ns")
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# Write to address 0x0 (should select inner1)
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inner1.AWREADY.value = 1
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inner1.WREADY.value = 1
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s_axil.AWVALID.value = 1
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s_axil.AWADDR.value = 0x0
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s_axil.WVALID.value = 1
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s_axil.WDATA.value = 0x12345678
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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assert int(inner1.AWVALID.value) == 1, "inner1 write address valid must be set"
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assert int(inner1.WVALID.value) == 1, "inner1 write data valid must be set"
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@cocotb.test()
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async def test_depth_2(dut):
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"""Test max_decode_depth=2 - should have interfaces for reg1 and inner2."""
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s_axil = _axil_slave(dut)
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# At depth 2, we should have m_axil_reg1 and m_axil_inner2
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reg1 = _axil_master(dut, "m_axil_reg1")
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inner2 = _axil_master(dut, "m_axil_inner2")
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# Default slave side inputs
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s_axil.AWVALID.value = 0
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s_axil.AWADDR.value = 0
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s_axil.AWPROT.value = 0
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s_axil.WVALID.value = 0
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s_axil.WDATA.value = 0
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s_axil.WSTRB.value = 0
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s_axil.BREADY.value = 0
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s_axil.ARVALID.value = 0
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s_axil.ARADDR.value = 0
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s_axil.ARPROT.value = 0
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s_axil.RREADY.value = 0
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for master in [reg1, inner2]:
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master.AWREADY.value = 0
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master.WREADY.value = 0
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master.BVALID.value = 0
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master.BRESP.value = 0
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master.ARREADY.value = 0
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master.RVALID.value = 0
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master.RDATA.value = 0
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master.RRESP.value = 0
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await Timer(1, units="ns")
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# Write to address 0x0 (should select reg1)
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reg1.AWREADY.value = 1
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reg1.WREADY.value = 1
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s_axil.AWVALID.value = 1
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s_axil.AWADDR.value = 0x0
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s_axil.WVALID.value = 1
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s_axil.WDATA.value = 0xABCDEF01
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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assert int(reg1.AWVALID.value) == 1, "reg1 must be selected for address 0x0"
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assert int(inner2.AWVALID.value) == 0, "inner2 should not be selected"
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# Reset
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s_axil.AWVALID.value = 0
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s_axil.WVALID.value = 0
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reg1.AWREADY.value = 0
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reg1.WREADY.value = 0
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await Timer(1, units="ns")
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# Write to address 0x10 (should select inner2)
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inner2.AWREADY.value = 1
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inner2.WREADY.value = 1
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s_axil.AWVALID.value = 1
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s_axil.AWADDR.value = 0x10
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s_axil.WVALID.value = 1
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s_axil.WDATA.value = 0x23456789
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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assert int(inner2.AWVALID.value) == 1, "inner2 must be selected for address 0x10"
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assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"
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@cocotb.test()
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async def test_depth_0(dut):
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"""Test max_decode_depth=0 - should have interfaces for all leaf registers."""
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s_axil = _axil_slave(dut)
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# At depth 0, we should have all leaf registers: reg1, reg2, reg2b
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reg1 = _axil_master(dut, "m_axil_reg1")
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reg2 = _axil_master(dut, "m_axil_reg2")
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reg2b = _axil_master(dut, "m_axil_reg2b")
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# Default slave side inputs
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s_axil.AWVALID.value = 0
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s_axil.AWADDR.value = 0
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s_axil.AWPROT.value = 0
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s_axil.WVALID.value = 0
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s_axil.WDATA.value = 0
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s_axil.WSTRB.value = 0
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s_axil.BREADY.value = 0
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s_axil.ARVALID.value = 0
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s_axil.ARADDR.value = 0
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s_axil.ARPROT.value = 0
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s_axil.RREADY.value = 0
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for master in [reg1, reg2, reg2b]:
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master.AWREADY.value = 0
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master.WREADY.value = 0
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master.BVALID.value = 0
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master.BRESP.value = 0
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master.ARREADY.value = 0
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master.RVALID.value = 0
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master.RDATA.value = 0
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master.RRESP.value = 0
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await Timer(1, units="ns")
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# Write to address 0x0 (should select reg1)
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reg1.AWREADY.value = 1
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reg1.WREADY.value = 1
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s_axil.AWVALID.value = 1
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s_axil.AWADDR.value = 0x0
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s_axil.WVALID.value = 1
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s_axil.WDATA.value = 0x11111111
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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assert int(reg1.AWVALID.value) == 1, "reg1 must be selected for address 0x0"
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assert int(reg2.AWVALID.value) == 0, "reg2 should not be selected"
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assert int(reg2b.AWVALID.value) == 0, "reg2b should not be selected"
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# Reset
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s_axil.AWVALID.value = 0
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s_axil.WVALID.value = 0
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reg1.AWREADY.value = 0
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reg1.WREADY.value = 0
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await Timer(1, units="ns")
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# Write to address 0x10 (should select reg2)
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reg2.AWREADY.value = 1
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reg2.WREADY.value = 1
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s_axil.AWVALID.value = 1
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s_axil.AWADDR.value = 0x10
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s_axil.WVALID.value = 1
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s_axil.WDATA.value = 0x22222222
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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assert int(reg2.AWVALID.value) == 1, "reg2 must be selected for address 0x10"
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assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"
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assert int(reg2b.AWVALID.value) == 0, "reg2b should not be selected"
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# Reset
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s_axil.AWVALID.value = 0
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s_axil.WVALID.value = 0
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reg2.AWREADY.value = 0
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reg2.WREADY.value = 0
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await Timer(1, units="ns")
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# Write to address 0x14 (should select reg2b)
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reg2b.AWREADY.value = 1
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reg2b.WREADY.value = 1
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s_axil.AWVALID.value = 1
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s_axil.AWADDR.value = 0x14
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s_axil.WVALID.value = 1
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s_axil.WDATA.value = 0x33333333
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s_axil.WSTRB.value = 0xF
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await Timer(1, units="ns")
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assert int(reg2b.AWVALID.value) == 1, "reg2b must be selected for address 0x14"
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assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"
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assert int(reg2.AWVALID.value) == 0, "reg2 should not be selected"
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128
tests/cocotb/axi4lite/smoke/test_variable_depth_runner.py
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128
tests/cocotb/axi4lite/smoke/test_variable_depth_runner.py
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@@ -0,0 +1,128 @@
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"""Pytest wrapper launching the AXI4-Lite cocotb smoke test for variable depth."""
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from pathlib import Path
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import pytest
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from peakrdl_busdecoder.cpuif.axi4lite.axi4_lite_cpuif_flat import AXI4LiteCpuifFlat
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try: # pragma: no cover - optional dependency shim
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from cocotb.runner import get_runner
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except ImportError: # pragma: no cover
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from cocotb_tools.runner import get_runner
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from tests.cocotb_lib.utils import compile_rdl_and_export, get_verilog_sources
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@pytest.mark.simulation
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@pytest.mark.verilator
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def test_axi4lite_variable_depth_1(tmp_path: Path) -> None:
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"""Test AXI4-Lite design with max_decode_depth=1."""
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repo_root = Path(__file__).resolve().parents[4]
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module_path, package_path = compile_rdl_and_export(
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str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
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"variable_depth",
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tmp_path,
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cpuif_cls=AXI4LiteCpuifFlat,
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max_decode_depth=1,
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)
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sources = get_verilog_sources(
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module_path,
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package_path,
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[repo_root / "hdl-src" / "axi4lite_intf.sv"],
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)
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runner = get_runner("verilator")
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build_dir = tmp_path / "sim_build"
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runner.build(
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sources=sources,
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hdl_toplevel=module_path.stem,
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build_dir=build_dir,
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)
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runner.test(
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hdl_toplevel=module_path.stem,
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test_module="tests.cocotb.axi4lite.smoke.test_variable_depth",
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build_dir=build_dir,
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log_file=str(tmp_path / "sim_depth1.log"),
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testcase="test_depth_1",
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)
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@pytest.mark.simulation
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@pytest.mark.verilator
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def test_axi4lite_variable_depth_2(tmp_path: Path) -> None:
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"""Test AXI4-Lite design with max_decode_depth=2."""
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repo_root = Path(__file__).resolve().parents[4]
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module_path, package_path = compile_rdl_and_export(
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str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
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"variable_depth",
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tmp_path,
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cpuif_cls=AXI4LiteCpuifFlat,
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max_decode_depth=2,
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)
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sources = get_verilog_sources(
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module_path,
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package_path,
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[repo_root / "hdl-src" / "axi4lite_intf.sv"],
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)
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runner = get_runner("verilator")
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build_dir = tmp_path / "sim_build"
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runner.build(
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sources=sources,
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hdl_toplevel=module_path.stem,
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build_dir=build_dir,
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)
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runner.test(
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hdl_toplevel=module_path.stem,
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test_module="tests.cocotb.axi4lite.smoke.test_variable_depth",
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build_dir=build_dir,
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log_file=str(tmp_path / "sim_depth2.log"),
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testcase="test_depth_2",
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)
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@pytest.mark.simulation
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@pytest.mark.verilator
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def test_axi4lite_variable_depth_0(tmp_path: Path) -> None:
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"""Test AXI4-Lite design with max_decode_depth=0 (all levels)."""
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repo_root = Path(__file__).resolve().parents[4]
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module_path, package_path = compile_rdl_and_export(
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str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
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"variable_depth",
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tmp_path,
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cpuif_cls=AXI4LiteCpuifFlat,
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max_decode_depth=0,
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)
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sources = get_verilog_sources(
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module_path,
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package_path,
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[repo_root / "hdl-src" / "axi4lite_intf.sv"],
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)
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runner = get_runner("verilator")
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build_dir = tmp_path / "sim_build"
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runner.build(
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sources=sources,
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hdl_toplevel=module_path.stem,
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build_dir=build_dir,
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)
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runner.test(
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hdl_toplevel=module_path.stem,
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test_module="tests.cocotb.axi4lite.smoke.test_variable_depth",
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build_dir=build_dir,
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log_file=str(tmp_path / "sim_depth0.log"),
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testcase="test_depth_0",
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)
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