bslathi19/PeakRDL-BusDecoder
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This commit is contained in:
Arnav Sacheti
2025-10-19 21:52:12 -07:00
parent bafebf8595
commit eb5e64b151
4 changed files with 2 additions and 4 deletions
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src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif_flat.py
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@@ -61,4 +61,3 @@ class APB3CpuifFlat(BaseCpuif):
if idx is not None: if idx is not None:
return f"{base}_{signal}[{idx}]" return f"{base}_{signal}[{idx}]"
return f"{base}_{signal}[N_{node.inst_name.upper()}S]" return f"{base}_{signal}[N_{node.inst_name.upper()}S]"

1
src/peakrdl_busdecoder/validate_design.py
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@@ -148,7 +148,6 @@ class DesignValidator(RDLListener):
node.inst.inst_src_ref, node.inst.inst_src_ref,
) )
def exit_AddressableComponent(self, node: AddressableNode) -> None: def exit_AddressableComponent(self, node: AddressableNode) -> None:
if not isinstance(node, RegNode): if not isinstance(node, RegNode):
# Exiting block-like node # Exiting block-like node