format

src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif_flat.py

@@ -61,4 +61,3 @@ class APB3CpuifFlat(BaseCpuif):
         if idx is not None:
             return f"{base}_{signal}[{idx}]"
         return f"{base}_{signal}[N_{node.inst_name.upper()}S]"
-

src/peakrdl_busdecoder/validate_design.py

@@ -148,7 +148,6 @@ class DesignValidator(RDLListener):
                     node.inst.inst_src_ref,
                 )
 
-
     def exit_AddressableComponent(self, node: AddressableNode) -> None:
         if not isinstance(node, RegNode):
             # Exiting block-like node