Gate assertions behind "PEAKRDL_ASSERTIONS define"

Add taxi apb interface
Downsize paddr bits
2025-11-22 16:34:52 -08:00 · 2025-11-22 15:56:18 -08:00 · 2025-11-22 12:26:32 -08:00
1 changed files with 2 additions and 2 deletions
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -4,9 +4,9 @@ build-backend = "setuptools.build_meta"
 [project]
 name = "peakrdl-busdecoder"
-version = "0.6.0"
+version = "0.5.0"
 requires-python = ">=3.10"
-dependencies = ["jinja2>=3.1.6", "systemrdl-compiler~=1.31"]
+dependencies = ["jinja2>=3.1.6", "systemrdl-compiler~=1.30.1"]
 authors = [{ name = "Arnav Sacheti" }]
 description = "Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces"
Author	SHA1	Message	Date
Byron Lathi	b0db1f60e4	Gate assertions behind "PEAKRDL_ASSERTIONS define"	2025-11-22 16:34:52 -08:00
Byron Lathi	b16eb33ee1	Add taxi apb interface	2025-11-22 15:56:18 -08:00
Byron Lathi	3c87510516	Downsize paddr bits	2025-11-22 12:26:32 -08:00