[build-system]
requires = ["setuptools", "setuptools-scm"]
build-backend = "setuptools.build_meta"

[project]
name = "peakrdl-busdecoder"
version = "0.1.0"
requires-python = ">=3.10"
dependencies = [
    "jinja2>=3.1.6",
    "systemrdl-compiler~=1.30.1",
]

authors = [{ name = "Alex Mykyta" }]
description = "Compile SystemRDL into a SystemVerilog control/status register (CSR) block"
readme = "README.md"
license = { text = "LGPLv3" }
keywords = [
    "SystemRDL",
    "PeakRDL",
    "CSR",
    "compiler",
    "tool",
    "registers",
    "generator",
    "Verilog",
    "SystemVerilog",
    "register abstraction layer",
    "FPGA",
    "ASIC",
]
classifiers = [
    "Development Status :: 5 - Production/Stable",
    "Programming Language :: Python",
    "Programming Language :: Python :: 3",
    "Programming Language :: Python :: 3 :: Only",
    "Intended Audience :: Developers",
    "License :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)",
    "Operating System :: OS Independent",
    "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
]

[project.optional-dependencies]
cli = ["peakrdl-cli >= 1.2.3"]

[project.urls]
Source = "https://github.com/SystemRDL/PeakRDL-busdecoder"
Tracker = "https://github.com/SystemRDL/PeakRDL-busdecoder/issues"
Changelog = "https://github.com/SystemRDL/PeakRDL-busdecoder/releases"
Documentation = "https://peakrdl-busdecoder.readthedocs.io/"

[dependency-groups]
docs = [
    "pygments-systemrdl>=1.3.0",
    "sphinx-book-theme>=1.1.4",
    "sphinxcontrib-wavedrom>=3.0.4",
]
test = [
    "parameterized>=0.9.0",
    "pytest>=7.4.4",
    "pytest-cov>=4.1.0",
    "pytest-xdist>=3.5.0",
]
tools = [
    "ruff>=0.14.0",
]

[project.entry-points."peakrdl.exporters"]
busdecoder = "peakrdl_busdecoder.__peakrdl__:Exporter"