/*
 * This file defines several property extensions that are understood by the
 * PeakRDL-BusDecoder SystemVerilog code generator.
 *
 * Compile this file prior to your other SystemRDL sources.
 *
 * For more details, see: https://peakrdl-busdecoder.readthedocs.io/en/latest/udps/intro.html
 */

property buffer_reads {
    component = reg;
    type = boolean;
};

property rbuffer_trigger {
    component = reg;
    type = ref;
};

property buffer_writes {
    component = reg;
    type = boolean;
};

property wbuffer_trigger {
    component = reg;
    type = ref;
};

property rd_swacc {
    component = field;
    type = boolean;
};

property wr_swacc {
    component = field;
    type = boolean;
};

property is_signed {
    type = boolean;
    component = field;
    default = true;
};

property intwidth {
    type = longint unsigned;
    component = field;
};

property fracwidth {
    type = longint unsigned;
    component = field;
};