addrmap top {
    reg my_reg {
        field {sw=rw; hw=r;} whatever[32] = 0;
    };
    reg my_reg_alt {
        field {sw=r; hw=w;} whatever_a[3:2] = 0;
        field {sw=w; hw=r;} whatever_b[4:4] = 0;
        field {sw=rw; hw=r;} whatever_c[15:8] = 0;
    };
    reg my_wide_reg {
        regwidth = 64;
        accesswidth = 32;
        field {sw=rw; hw=r;} whatever = 0;
    };

    external my_reg_alt ext_reg @ 0x00;
    my_reg int_reg @ 0x04;
    external my_wide_reg wide_ext_reg @ 0x10;
    external my_reg ext_reg_array[32] @ 0x100 += 4;


    external regfile {
        my_reg placeholder @ 8*4-4;
    } rf @ 0x1000;

    addrmap {
        my_reg placeholder @ 8*4-4;
    } am @ 0x2000;

    external mem {
        memwidth = 32;
        mementries = 8;
    } mm @ 0x3000;

    reg my_ro_reg {
        field {sw=r; hw=w;} whatever[32] = 0;
    };
    reg my_wo_reg {
        field {sw=w; hw=r;} whatever[32] = 0;
    };
    external my_ro_reg ro_reg @ 0x4000;
    external my_wo_reg wo_reg @ 0x4004;

    reg my_wide_ro_reg {
        regwidth = 64;
        accesswidth = 32;
        field {sw=r; hw=w;} whatever[32] = 0;
    };
    reg my_wide_wo_reg {
        regwidth = 64;
        accesswidth = 32;
        field {sw=w; hw=r;} whatever[32] = 0;
    };
    external my_wide_ro_reg wide_ro_reg @ 0x4010;
    external my_wide_wo_reg wide_wo_reg @ 0x4018;
};