62 lines
1.9 KiB
ReStructuredText
62 lines
1.9 KiB
ReStructuredText
Hardware Interface
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------------------
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The generated register block will present the entire hardware interface to the user
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using two struct ports:
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* ``hwif_in``
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* ``hwif_out``
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All field inputs and outputs as well as signals are consolidated into these
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struct ports. The presence of each depends on the specific contents of the design
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being exported.
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Using structs for the hardware interface has the following benefits:
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* Preserves register map component grouping, arrays, and hierarchy.
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* Avoids naming collisions and cumbersome signal name flattening.
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* Allows for more natural mapping and distribution of register block signals to a design's hardware components.
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* Use of unpacked arrays/structs prevents common assignment mistakes as they are enforced by the compiler.
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Structs are organized as follows: ``hwif_out.<heir_path>.<feature>``
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For example, a simple design such as:
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.. code-block:: systemrdl
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addrmap my_design {
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reg {
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field {
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sw = rw;
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hw = rw;
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we;
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} my_field;
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} my_reg[2];
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};
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... results in the following struct members:
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.. code-block:: text
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hwif_out.my_reg[0].my_field.value
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hwif_in.my_reg[0].my_field.next
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hwif_in.my_reg[0].my_field.we
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hwif_out.my_reg[1].my_field.value
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hwif_in.my_reg[1].my_field.next
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hwif_in.my_reg[1].my_field.we
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For brevity in this documentation, hwif features will be described using shorthand
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notation that omits the hierarchical path: ``hwif_out..<feature>``
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.. important::
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The PeakRDL tool makes no guarantees on the field order of the hwif structs.
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For this reason, it is strongly recommended to always access struct members
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directly, by name.
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If using the SystemVerilog streaming operator to assign the hwif struct to a
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packed vector, be extremely careful to avoid assumptions on the resulting bit-position of a field.
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