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* Initial plan * Update documentation to use correct repository name PeakRDL-BusDecoder Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Update CONTRIBUTING.md and GitHub templates with correct repository name Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Update author to arnavsacheti and clarify bus decoder purpose in documentation Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Update author to 'Arnav Sacheti' and revise UDP documentation to reflect no current UDP support Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
98 lines
2.7 KiB
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98 lines
2.7 KiB
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Introduction
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============
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PeakRDL-BusDecoder is a free and open-source bus decoder generator for hierarchical register address maps.
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This code generator translates your SystemRDL register description into a synthesizable
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SystemVerilog RTL module that decodes CPU interface transactions and routes them to
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multiple sub-address spaces (child addrmaps). This is particularly useful for:
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* Creating hierarchical register maps with multiple sub-components
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* Splitting a single CPU interface bus to serve multiple independent register blocks
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* Organizing large register designs into logical sub-address spaces
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* Implementing address decode logic for multi-drop bus architectures
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The generated bus decoder provides:
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* Fully synthesizable SystemVerilog RTL (IEEE 1800-2012)
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* Support for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
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* Address decode logic that routes transactions to child address maps
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* Configurable pipelining options for designs with fast clock rates
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* Broad support for SystemRDL 2.0 features
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Quick Start
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-----------
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The easiest way to use PeakRDL-BusDecoder is via the `PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_:
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.. code-block:: bash
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# Install PeakRDL-BusDecoder along with the command-line tool
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python3 -m pip install peakrdl-busdecoder[cli]
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# Export!
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peakrdl busdecoder atxmega_spi.rdl -o busdecoder/ --cpuif axi4-lite
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Looking for VHDL?
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-----------------
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This project generates SystemVerilog RTL. If you prefer using VHDL, check out
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the sister project which aims to be a feature-equivalent fork of
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PeakRDL-BusDecoder: `PeakRDL-busdecoder-VHDL <https://peakrdl-busdecoder-vhdl.readthedocs.io>`_
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Links
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-----
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- `Source repository <https://github.com/arnavsacheti/PeakRDL-BusDecoder>`_
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- `Release Notes <https://github.com/arnavsacheti/PeakRDL-BusDecoder/releases>`_
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- `Issue tracker <https://github.com/arnavsacheti/PeakRDL-BusDecoder/issues>`_
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- `PyPi <https://pypi.org/project/peakrdl-busdecoder>`_
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- `SystemRDL Specification <http://accellera.org/downloads/standards/systemrdl>`_
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.. toctree::
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:hidden:
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self
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architecture
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hwif
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configuring
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limitations
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faq
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licensing
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api
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.. toctree::
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:hidden:
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:caption: CPU Interfaces
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cpuif/introduction
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cpuif/apb
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cpuif/axi4lite
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cpuif/avalon
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cpuif/passthrough
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cpuif/internal_protocol
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cpuif/customizing
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.. toctree::
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:hidden:
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:caption: SystemRDL Properties
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props/field
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props/reg
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props/addrmap
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props/signal
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props/rhs_props
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.. toctree::
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:hidden:
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:caption: Other SystemRDL Features
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rdl_features/external
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.. toctree::
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:hidden:
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:caption: Extended Properties
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udps/intro
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