57 lines
1.0 KiB
Systemverilog
57 lines
1.0 KiB
Systemverilog
interface apb4_intf #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 32
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);
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// Clocking
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logic PCLK;
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logic PRESETn;
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// Command
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logic PSEL;
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logic PENABLE;
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logic PWRITE;
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logic [2:0] PPROT;
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logic [ADDR_WIDTH-1:0] PADDR;
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logic [DATA_WIDTH-1:0] PWDATA;
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logic [DATA_WIDTH/8-1:0] PSTRB;
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// Response
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logic [DATA_WIDTH-1:0] PRDATA;
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logic PREADY;
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logic PSLVERR;
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modport master (
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input PCLK,
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input PRESETn,
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output PSEL,
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output PENABLE,
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output PWRITE,
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output PPROT,
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output PADDR,
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output PWDATA,
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output PSTRB,
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input PRDATA,
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input PREADY,
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input PSLVERR
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);
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modport slave (
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input PCLK,
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input PRESETn,
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input PSEL,
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input PENABLE,
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input PWRITE,
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input PPROT,
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input PADDR,
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input PWDATA,
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input PSTRB,
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output PRDATA,
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output PREADY,
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output PSLVERR
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);
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endinterface
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